From patchwork Tue Dec 4 09:25:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10711365 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA31618A7 for ; Tue, 4 Dec 2018 09:27:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC2122AC6D for ; Tue, 4 Dec 2018 09:27:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D03D72AD0A; Tue, 4 Dec 2018 09:27:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 824AC2ACDA for ; Tue, 4 Dec 2018 09:27:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tGrQXvPeKJoHVsnrppnbNtpdhPskPEcg/GlVvcC/Ud4=; b=poSZMSTGjdsicK 3gbn2zPswrtpsIu4biwrMcsfHW3nPF1RpHcj5JnYJr/ilAv89A7mfdzQJawBDAnrO5JIo6zYF0bZ7 JS42usg5PC1DI8HJOmY1SrYNpKxE9dyY/gQJHTGUlgNDtYiI13R2XDv3msU/W7goOgiMhhG3uArUc nWd+cyKfKUEWy/J9FjxWN/jhqNKdIW8t/6ANRwy3ju1iUCwUUuR+IeaiKv8vGcdd9Ge6LWQdp3H9W jI325ARZscmUsm++D+NAXfGqKRFE4MKcTNtVB3fq3YIsYwc4g8u/J4l0QSsoCfvpN+EKNIkUHEEUT Amntl0NMsdx0Fmfuodbw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gU6yt-00007M-4Y; Tue, 04 Dec 2018 09:27:03 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gU6yb-000838-Pk for linux-arm-kernel@lists.infradead.org; Tue, 04 Dec 2018 09:26:51 +0000 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:26:37 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:26:35 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 04 Dec 2018 01:26:35 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:34 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:34 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:34 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter Subject: [PATCH 02/19] dt-bindings: clock: tegra124-dfll: add Tegra210 support Date: Tue, 4 Dec 2018 17:25:31 +0800 Message-ID: <20181204092548.3038-3-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915597; bh=c0gDJI0oagMAfW/bVTl/FY193pIwoFOy3oJkr8g4I14=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=eFM3SH/plzlnauZ0/4IHgLk4dAjZZkrD1IY0W9PrG5a8kOrd9+C+RmkZOZKZT9Y56 +mnuwypoffFbjTh9yYmV47mX5SG0Xb4J4MPoqHjLOQk5iVdP9szVAlqUkTWO2102fQ MzT73SvwyWxk4LyLbflrHTuiWN7p7TlOw7W+/8zhDR34z6FjmI46wf0bZ9au7mZExF VLU2QXrZVXYRqmTJrXX4+sNhR2YdOTN/f7cDrbdGGCL5rC5ZwXfmBGjImBBm7PQgM6 MatPM14skGSUfqZ4AN/DC5cMcA507uCBcWUFM2NCUJ4KUEWodWhuPn0i+FaxYIm/dE FHLF/++V7JCww== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181204_012646_614482_54A2F06C X-CRM114-Status: UNSURE ( 9.30 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add Tegra210 support for DFLL clock. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- .../devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 8c97600d2bad..4bd44dd7ec1e 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -10,7 +10,9 @@ control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. Required properties: -- compatible : should be "nvidia,tegra124-dfll" +- compatible : should be one of: + - "nvidia,tegra124-dfll": for Tegra124 + - "nvidia,tegra210-dfll": for Tegra210 - reg : Defines the following set of registers, in the order listed: - registers for the DFLL control logic. - registers for the I2C output logic.