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Tue, 4 Dec 2018 09:26:53 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 04 Dec 2018 01:26:52 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter Subject: [PATCH 08/19] clk: tegra: dfll: round down voltages based on alignment Date: Tue, 4 Dec 2018 17:25:37 +0800 Message-ID: <20181204092548.3038-9-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915613; bh=76SiM3Sn+CKXxnGOoZ1qarCkO2okk2A7hMW12Zz3zNE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=FOn/aDweCHSUq4A7eXN0Yk2jGGZuW62H+EQFkH+DDwDH5uBaAQG79+zraSc/jGvID QBN/uHeV4cV4PrFnnD1zSP+X1M4kpSFWmK1Ztx3HNbi08v1pYp/f++9jUfT063RO3C IjkLf/ZMCbsp55yBjb+IMQPzIAcEt3tHJqC59qhCpkk5FMQAYwPLF19scRQb3X9LGo EkWfxNFuXx6lZAyiUdbpghNAk/AobUyl6Cf1yhqf018/sv1NYIPuOyAMV0t5zq4Njn MUQ4xTcT8qyComwN/Rca5/DxBwWPJ5m3fIoXomiIZ4O6u1y4U8tqQBM/yddob/PCO0 BjeIXETy4Ta0g== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181204_012705_168335_6535935A X-CRM114-Status: GOOD ( 11.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP When generating the OPP table, the voltages are round down with the alignment from the regulator. The alignment should be applied for voltages look up as well. Based on the work of Penny Chiu . Signed-off-by: Joseph Lo --- drivers/clk/tegra/clk-dfll.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index c294a2989f31..4a943c136d4d 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -804,17 +804,17 @@ static void dfll_init_out_if(struct tegra_dfll *td) static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) { struct dev_pm_opp *opp; - int i, uv; + int i, align_volt; opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); if (IS_ERR(opp)) return PTR_ERR(opp); - uv = dev_pm_opp_get_voltage(opp); + align_volt = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv; dev_pm_opp_put(opp); for (i = td->lut_bottom; i < td->lut_size; i++) { - if (regulator_list_voltage(td->vdd_reg, td->lut[i]) == uv) + if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_volt) return i; } @@ -1532,15 +1532,17 @@ static int dfll_init(struct tegra_dfll *td) */ static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) { - int i, n_voltages, reg_uV; + int i, n_voltages, reg_volt, align_volt; + align_volt = uV / td->soc->alignment.step_uv; n_voltages = regulator_count_voltages(td->vdd_reg); for (i = 0; i < n_voltages; i++) { - reg_uV = regulator_list_voltage(td->vdd_reg, i); - if (reg_uV < 0) + reg_volt = regulator_list_voltage(td->vdd_reg, i) / + td->soc->alignment.step_uv; + if (reg_volt < 0) break; - if (uV == reg_uV) + if (align_volt == reg_volt) return i; } @@ -1554,15 +1556,17 @@ static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) * */ static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) { - int i, n_voltages, reg_uV; + int i, n_voltages, reg_volt, align_volt; + align_volt = uV / td->soc->alignment.step_uv; n_voltages = regulator_count_voltages(td->vdd_reg); for (i = 0; i < n_voltages; i++) { - reg_uV = regulator_list_voltage(td->vdd_reg, i); - if (reg_uV < 0) + reg_volt = regulator_list_voltage(td->vdd_reg, i) / + td->soc->alignment.step_uv; + if (reg_volt < 0) break; - if (uV <= reg_uV) + if (align_volt <= reg_volt) return i; }