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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id o8sm55023141pfa.42.2018.12.05.23.31.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 05 Dec 2018 23:31:47 -0800 (PST) From: Andrey Smirnov To: Marc Zyngier Subject: [PATCH 3/5] irqchip/irq-imx-gpcv2: Make use of BIT() macro Date: Wed, 5 Dec 2018 23:31:23 -0800 Message-Id: <20181206073125.7255-4-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181206073125.7255-1-andrew.smirnov@gmail.com> References: <20181206073125.7255-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181205_233200_368161_3B7DD768 X-CRM114-Status: GOOD ( 13.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "A.s. Dong" , Richard Zhu , Jason Cooper , linux-arm-kernel@lists.infradead.org, Andrey Smirnov , linux-kernel@vger.kernel.org, linux-imx@nxp.com, Thomas Gleixner , Leonard Crestez , cphealy@gmail.com, l.stach@pengutronix.de Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Convert all instances of 1 << x to BIT(x) for consistency with other kernel code. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach --- drivers/irqchip/irq-imx-gpcv2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index b262ba8b2652..077d56b3183a 100644 --- a/drivers/irqchip/irq-imx-gpcv2.c +++ b/drivers/irqchip/irq-imx-gpcv2.c @@ -78,7 +78,7 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) u32 mask, val; raw_spin_lock_irqsave(&cd->rlock, flags); - mask = 1 << d->hwirq % 32; + mask = BIT(d->hwirq % 32); val = cd->wakeup_sources[idx]; cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask); @@ -101,7 +101,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d) raw_spin_lock(&cd->rlock); reg = gpcv2_idx_to_reg(cd, d->hwirq / 32); val = readl_relaxed(reg); - val &= ~(1 << d->hwirq % 32); + val &= ~BIT(d->hwirq % 32); writel_relaxed(val, reg); raw_spin_unlock(&cd->rlock); @@ -117,7 +117,7 @@ static void imx_gpcv2_irq_mask(struct irq_data *d) raw_spin_lock(&cd->rlock); reg = gpcv2_idx_to_reg(cd, d->hwirq / 32); val = readl_relaxed(reg); - val |= 1 << (d->hwirq % 32); + val |= BIT(d->hwirq % 32); writel_relaxed(val, reg); raw_spin_unlock(&cd->rlock);