| Message ID | 20181223235836.12466-2-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: meson8b: fix typo "ABP" -> "APB" | expand |
Quoting Martin Blumenstingl (2018-12-23 15:58:36) > Fix a typo in the APB clock names by renaming them from "abp" to "apb". > No functional changes. > > Fixes: 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") > Fixes: a7d19b05ce817d ("clk: meson: meson8b: add the CPU clock post divider clocks") > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- Can I apply this directly to fixes? Or it's not critical so we can punt until next merge window?
Hi Stephen, Hi Neil, On Wed, Jan 9, 2019 at 7:43 PM Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Martin Blumenstingl (2018-12-23 15:58:36) > > Fix a typo in the APB clock names by renaming them from "abp" to "apb". > > No functional changes. > > > > Fixes: 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") > > Fixes: a7d19b05ce817d ("clk: meson: meson8b: add the CPU clock post divider clocks") > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > --- > > Can I apply this directly to fixes? Or it's not critical so we can punt > until next merge window? actually it's not critical: I'm not aware of any IP block that I needs the APB clock as input (I'm pretty sure there is some, but I'm not aware of it so it can wait). Neil already applied another patch for -next which conflicts with this. we can choose now: 1. Stephen takes this patch, Neil drops the (conflicting) GPU clock patches from -next and I re-send the GPU clock patches 2. Stephen and Neil don't do anything, I re-send this patch on top of the GPU clock patches I'm fine either way, but #2 is less work for you guys. if I don't hear back from you then I'll go with option #2 Regards Martin
Quoting Martin Blumenstingl (2019-01-09 14:30:24) > Hi Stephen, Hi Neil, > > On Wed, Jan 9, 2019 at 7:43 PM Stephen Boyd <sboyd@kernel.org> wrote: > > > > Quoting Martin Blumenstingl (2018-12-23 15:58:36) > > > Fix a typo in the APB clock names by renaming them from "abp" to "apb". > > > No functional changes. > > > > > > Fixes: 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") > > > Fixes: a7d19b05ce817d ("clk: meson: meson8b: add the CPU clock post divider clocks") > > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > > --- > > > > Can I apply this directly to fixes? Or it's not critical so we can punt > > until next merge window? > actually it's not critical: > I'm not aware of any IP block that I needs the APB clock as input (I'm > pretty sure there is some, but I'm not aware of it so it can wait). > > Neil already applied another patch for -next which conflicts with this. > we can choose now: > 1. Stephen takes this patch, Neil drops the (conflicting) GPU clock > patches from -next and I re-send the GPU clock patches > 2. Stephen and Neil don't do anything, I re-send this patch on top of > the GPU clock patches > > I'm fine either way, but #2 is less work for you guys. > if I don't hear back from you then I'll go with option #2 If it's not critical then I'll let it go via the normal paths through Neil's tree.
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 950d0e548c75..fa15ba9f4327 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -803,16 +803,16 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = { }, }; -static u32 mux_table_abp[] = { 1, 2, 3, 4, 5, 6, 7 }; -static struct clk_regmap meson8b_abp_clk_sel = { +static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 }; +static struct clk_regmap meson8b_apb_clk_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .mask = 0x7, .shift = 3, - .table = mux_table_abp, + .table = mux_table_apb, }, .hw.init = &(struct clk_init_data){ - .name = "abp_clk_sel", + .name = "apb_clk_sel", .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cpu_clk_div2", "cpu_clk_div3", @@ -825,16 +825,16 @@ static struct clk_regmap meson8b_abp_clk_sel = { }, }; -static struct clk_regmap meson8b_abp_clk_gate = { +static struct clk_regmap meson8b_apb_clk_gate = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 16, .flags = CLK_GATE_SET_TO_DISABLE, }, .hw.init = &(struct clk_init_data){ - .name = "abp_clk_dis", + .name = "apb_clk_dis", .ops = &clk_regmap_gate_ro_ops, - .parent_names = (const char *[]){ "abp_clk_sel" }, + .parent_names = (const char *[]){ "apb_clk_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, }, @@ -1781,8 +1781,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, - [CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw, - [CLKID_ABP] = &meson8b_abp_clk_gate.hw, + [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, + [CLKID_APB] = &meson8b_apb_clk_gate.hw, [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, @@ -1943,8 +1943,8 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_fixed_pll_dco, &meson8b_hdmi_pll_dco, &meson8b_sys_pll_dco, - &meson8b_abp_clk_sel, - &meson8b_abp_clk_gate, + &meson8b_apb_clk_sel, + &meson8b_apb_clk_gate, &meson8b_periph_clk_sel, &meson8b_periph_clk_gate, &meson8b_axi_clk_sel, diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 87fba739af81..3cac2be7138b 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -91,7 +91,7 @@ #define CLKID_CPU_CLK_DIV6 120 #define CLKID_CPU_CLK_DIV7 121 #define CLKID_CPU_CLK_DIV8 122 -#define CLKID_ABP_SEL 123 +#define CLKID_APB_SEL 123 #define CLKID_PERIPH_SEL 125 #define CLKID_AXI_SEL 127 #define CLKID_L2_DRAM_SEL 129 diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 5fe2923382d0..cd11628f50f8 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -103,7 +103,7 @@ #define CLKID_MPLL1 94 #define CLKID_MPLL2 95 #define CLKID_NAND_CLK 112 -#define CLKID_ABP 124 +#define CLKID_APB 124 #define CLKID_PERIPH 126 #define CLKID_AXI 128 #define CLKID_L2_DRAM 130
Fix a typo in the APB clock names by renaming them from "abp" to "apb". No functional changes. Fixes: 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") Fixes: a7d19b05ce817d ("clk: meson: meson8b: add the CPU clock post divider clocks") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/meson/meson8b.c | 22 +++++++++++----------- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 2 +- 3 files changed, 13 insertions(+), 13 deletions(-)