| Message ID | 20190114170316.GB4168@bogon.m.sigxcpu.org (mailing list archive) |
|---|---|
| State | Mainlined, archived |
| Commit | a0e046e642b1f0a64da6d78d9fdc42d9845b07f6 |
| Headers | show |
| Series | [v2] arm64: dts: imx8mq: Add pwm | expand |
Am Montag, den 14.01.2019, 18:03 +0100 schrieb Guido Günther: > We can reuse the pwm from fsl,imx27-pwm as with other imx SOCs. > > Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > Changes from v1 (thanks Lucas Stach for the review): > - fix indentation of multine entries > - move to AIPS2 bus > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 44 +++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 8e9d6d5ed7b2..0b42fcb1ecaa 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -259,6 +259,50 @@ > > #address-cells = <1>; > > #size-cells = <1>; > > ranges = <0x30400000 0x30400000 0x400000>; > + > > > + pwm1: pwm@30660000 { > > + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; > > + reg = <0x30660000 0x10000>; > > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, > > + <&clk IMX8MQ_CLK_PWM1_ROOT>; > > + clock-names = "ipg", "per"; > > + #pwm-cells = <2>; > > + status = "disabled"; > > + }; > + > > > + pwm2: pwm@30670000 { > > + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; > > + reg = <0x30670000 0x10000>; > > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, > > + <&clk IMX8MQ_CLK_PWM2_ROOT>; > > + clock-names = "ipg", "per"; > > + #pwm-cells = <2>; > > + status = "disabled"; > > + }; > + > > > + pwm3: pwm@30680000 { > > + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; > > + reg = <0x30680000 0x10000>; > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, > > + <&clk IMX8MQ_CLK_PWM3_ROOT>; > > + clock-names = "ipg", "per"; > > + #pwm-cells = <2>; > > + status = "disabled"; > > + }; > + > > > + pwm4: pwm@30690000 { > > + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; > > + reg = <0x30690000 0x10000>; > > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, > > + <&clk IMX8MQ_CLK_PWM4_ROOT>; > > + clock-names = "ipg", "per"; > > + #pwm-cells = <2>; > > + status = "disabled"; > > + }; > > }; > > > bus@30800000 { /* AIPS3 */
On Mon, Jan 14, 2019 at 06:03:16PM +0100, Guido Günther wrote: > We can reuse the pwm from fsl,imx27-pwm as with other imx SOCs. > > Signed-off-by: Guido Günther <agx@sigxcpu.org> Applied, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 8e9d6d5ed7b2..0b42fcb1ecaa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -259,6 +259,50 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x30400000 0x30400000 0x400000>; + + pwm1: pwm@30660000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, + <&clk IMX8MQ_CLK_PWM1_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, + <&clk IMX8MQ_CLK_PWM2_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, + <&clk IMX8MQ_CLK_PWM3_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, + <&clk IMX8MQ_CLK_PWM4_ROOT>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; }; bus@30800000 { /* AIPS3 */
We can reuse the pwm from fsl,imx27-pwm as with other imx SOCs. Signed-off-by: Guido Günther <agx@sigxcpu.org> --- Changes from v1 (thanks Lucas Stach for the review): - fix indentation of multine entries - move to AIPS2 bus arch/arm64/boot/dts/freescale/imx8mq.dtsi | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+)