| Message ID | 20190115110325.13236-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] arm64: dts: fsl: imx8mq: add USB nodes | expand |
Hi Lucas, > -----Original Message----- > From: Lucas Stach <l.stach@pengutronix.de> > Sent: 2019年1月15日 19:03 > To: Shawn Guo <shawnguo@kernel.org> > Cc: Fabio Estevam <fabio.estevam@nxp.com>; dl-linux-imx <linux-imx@nxp.com>; > linux-arm-kernel@lists.infradead.org; kernel@pengutronix.de; > patchwork-lst@pengutronix.de > Subject: [PATCH 1/2] arm64: dts: fsl: imx8mq: add USB nodes > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 66 +++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 5bd1f106ed84..d25ab50d6b88 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -470,6 +470,72 @@ > }; > }; > > + usb_dwc3_0: usb@38100000 { > + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; > + reg = <0x38100000 0x10000>; > + clocks = <&clk IMX8MQ_CLK_USB_BUS>, > + <&clk IMX8MQ_CLK_USB_CORE_REF>, > + <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; > + clock-names = "bus_early", "ref", "suspend"; > + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, > + <&clk IMX8MQ_CLK_USB_CORE_REF>; > + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, > + <&clk IMX8MQ_SYS1_PLL_100M>; > + assigned-clock-rates = <500000000>, <100000000>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_phy0>, <&usb3_phy0>; > + phy-names = "usb2-phy", "usb3-phy"; > + power-domains = <&pgc_otg1>; > + snps,power-down-scale = <2>; This property does not exist on upstream, need firstly introduce it for dwc3 driver before add it in dts, I can do that if you are not going to take care of it. Jun > + usb3-resume-missing-cas; > + status = "disabled"; > + }; > + > + usb3_phy0: phy@381f0040 { > + compatible = "fsl,imx8mq-usb-phy"; > + reg = <0x381f0040 0x40>; > + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; > + clock-names = "phy"; > + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; > + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; > + assigned-clock-rates = <100000000>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + usb_dwc3_1: usb@38200000 { > + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; > + reg = <0x38200000 0x10000>; > + clocks = <&clk IMX8MQ_CLK_USB_BUS>, > + <&clk IMX8MQ_CLK_USB_CORE_REF>, > + <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; > + clock-names = "bus_early", "ref", "suspend"; > + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, > + <&clk IMX8MQ_CLK_USB_CORE_REF>; > + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, > + <&clk IMX8MQ_SYS1_PLL_100M>; > + assigned-clock-rates = <500000000>, <100000000>; > + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_phy1>, <&usb3_phy1>; > + phy-names = "usb2-phy", "usb3-phy"; > + power-domains = <&pgc_otg2>; > + snps,power-down-scale = <2>; Ditto > + usb3-resume-missing-cas; > + status = "disabled"; > + }; > + > + usb3_phy1: phy@382f0040 { > + compatible = "fsl,imx8mq-usb-phy"; > + reg = <0x382f0040 0x40>; > + clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; > + clock-names = "phy"; > + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; > + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; > + assigned-clock-rates = <100000000>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, /* GIC Dist */ > -- > 2.20.1
Hi Jun, Am Mittwoch, den 16.01.2019, 04:30 +0000 schrieb Jun Li: > Hi Lucas, > > -----Original Message----- > > > > From: Lucas Stach <l.stach@pengutronix.de> > > Sent: 2019年1月15日 19:03 > > > > To: Shawn Guo <shawnguo@kernel.org> > > > > Cc: Fabio Estevam <fabio.estevam@nxp.com>; dl-linux-imx <linux-imx@nxp.com>; > > > > linux-arm-kernel@lists.infradead.org; kernel@pengutronix.de; > > patchwork-lst@pengutronix.de > > Subject: [PATCH 1/2] arm64: dts: fsl: imx8mq: add USB nodes > > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 66 +++++++++++++++++++++++ > > 1 file changed, 66 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > index 5bd1f106ed84..d25ab50d6b88 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > @@ -470,6 +470,72 @@ > > > > }; > > > > }; > > > > > > > > + usb_dwc3_0: usb@38100000 { > > > > + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; > > > > + reg = <0x38100000 0x10000>; > > > > + clocks = <&clk IMX8MQ_CLK_USB_BUS>, > > > > + <&clk IMX8MQ_CLK_USB_CORE_REF>, > > > > + <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; > > > > + clock-names = "bus_early", "ref", "suspend"; > > > > + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, > > > > + <&clk IMX8MQ_CLK_USB_CORE_REF>; > > > > + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, > > > > + <&clk IMX8MQ_SYS1_PLL_100M>; > > > > + assigned-clock-rates = <500000000>, <100000000>; > > > > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > > > > + phys = <&usb3_phy0>, <&usb3_phy0>; > > > > + phy-names = "usb2-phy", "usb3-phy"; > > > > + power-domains = <&pgc_otg1>; > > + snps,power-down-scale = <2>; > > This property does not exist on upstream, need firstly introduce it for dwc3 driver > before add it in dts, I can do that if you are not going to take care of it. I'm going to remove this from this patch in the next revision. I'm not sure when I'm going to get around to look more at USB, so please CC me if/when you are introducing this to the DWC3 driver. Regards, Lucas
On Tue, Jan 15, 2019 at 12:03:24PM +0100, Lucas Stach wrote: > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 66 +++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 5bd1f106ed84..d25ab50d6b88 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -470,6 +470,72 @@ > }; > }; > > + usb_dwc3_0: usb@38100000 { > + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; We should document the compatible even though it's not used by kernel for now. Shawn > + reg = <0x38100000 0x10000>; > + clocks = <&clk IMX8MQ_CLK_USB_BUS>, > + <&clk IMX8MQ_CLK_USB_CORE_REF>, > + <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; > + clock-names = "bus_early", "ref", "suspend"; > + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, > + <&clk IMX8MQ_CLK_USB_CORE_REF>; > + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, > + <&clk IMX8MQ_SYS1_PLL_100M>; > + assigned-clock-rates = <500000000>, <100000000>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_phy0>, <&usb3_phy0>; > + phy-names = "usb2-phy", "usb3-phy"; > + power-domains = <&pgc_otg1>; > + snps,power-down-scale = <2>; > + usb3-resume-missing-cas; > + status = "disabled"; > + }; > + > + usb3_phy0: phy@381f0040 { > + compatible = "fsl,imx8mq-usb-phy"; > + reg = <0x381f0040 0x40>; > + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; > + clock-names = "phy"; > + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; > + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; > + assigned-clock-rates = <100000000>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + usb_dwc3_1: usb@38200000 { > + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; > + reg = <0x38200000 0x10000>; > + clocks = <&clk IMX8MQ_CLK_USB_BUS>, > + <&clk IMX8MQ_CLK_USB_CORE_REF>, > + <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; > + clock-names = "bus_early", "ref", "suspend"; > + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, > + <&clk IMX8MQ_CLK_USB_CORE_REF>; > + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, > + <&clk IMX8MQ_SYS1_PLL_100M>; > + assigned-clock-rates = <500000000>, <100000000>; > + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_phy1>, <&usb3_phy1>; > + phy-names = "usb2-phy", "usb3-phy"; > + power-domains = <&pgc_otg2>; > + snps,power-down-scale = <2>; > + usb3-resume-missing-cas; > + status = "disabled"; > + }; > + > + usb3_phy1: phy@382f0040 { > + compatible = "fsl,imx8mq-usb-phy"; > + reg = <0x382f0040 0x40>; > + clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; > + clock-names = "phy"; > + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; > + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; > + assigned-clock-rates = <100000000>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, /* GIC Dist */ > -- > 2.20.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5bd1f106ed84..d25ab50d6b88 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -470,6 +470,72 @@ }; }; + usb_dwc3_0: usb@38100000 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + reg = <0x38100000 0x10000>; + clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>, + <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&pgc_otg1>; + snps,power-down-scale = <2>; + usb3-resume-missing-cas; + status = "disabled"; + }; + + usb3_phy0: phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x381f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb_dwc3_1: usb@38200000 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + reg = <0x38200000 0x10000>; + clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>, + <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, + <&clk IMX8MQ_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <500000000>, <100000000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&pgc_otg2>; + snps,power-down-scale = <2>; + usb3-resume-missing-cas; + status = "disabled"; + }; + + usb3_phy1: phy@382f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x382f0040 0x40>; + clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; + assigned-clock-rates = <100000000>; + #phy-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 66 +++++++++++++++++++++++ 1 file changed, 66 insertions(+)