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Mon, 28 Jan 2019 06:08:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akkea.ca; s=mail; t=1548655729; bh=YV7evlfUpCm1dkvzmR2FsHaiKUjwEqKtN/TqcgcdxSQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=AYl266RKyavEpchUQ7VdxF8gWoIOz62hfuG0qlo8VEbXqHNPlXjvRXgGMgYMWnmfQ 8+2CLC9mo6dXmPcmnSVwyuCIEQRCCZ9fBMZBHYLNM2U2u5VFQbvxS0yxBjmRVnO9sK XNbdsvampUauH5ZFMc2nx6aG8Z35AI+42MjWqpVE= From: "Angus Ainslie (Purism)" To: angus@akkea.ca Subject: [PATCH v5 1/5] dmaengine: imx-sdma: add clock ratio 1:1 check Date: Sun, 27 Jan 2019 23:08:36 -0700 Message-Id: <20190128060840.31695-2-angus@akkea.ca> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190128060840.31695-1-angus@akkea.ca> References: <20190120023150.17138-1-angus@akkea.ca> <20190128060840.31695-1-angus@akkea.ca> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190127_220850_341549_EA1871D4 X-CRM114-Status: GOOD ( 10.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Baluta , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul , NXP Linux Team , Pengutronix Kernel Team , angus.ainslie@puri.sm, linux-arm-kernel@lists.infradead.org, Lucas Stach MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted, since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach to 500Mhz, so use 1:1 instead. Based on NXP commit MLK-16841-1 by Robin Gong Signed-off-by: Angus Ainslie (Purism) Reviewed-by: Lucas Stach --- drivers/dma/imx-sdma.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 0b3a67ff8e82..757fad2fbfae 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -440,6 +440,8 @@ struct sdma_engine { unsigned int irq; dma_addr_t bd0_phys; struct sdma_buffer_descriptor *bd0; + /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ + bool clk_ratio; }; static int sdma_config_write(struct dma_chan *chan, @@ -662,8 +664,11 @@ static int sdma_run_channel0(struct sdma_engine *sdma) dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); /* Set bits of CONFIG register with dynamic context switching */ - if (readl(sdma->regs + SDMA_H_CONFIG) == 0) - writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); + reg = readl(sdma->regs + SDMA_H_CONFIG); + if ((reg & SDMA_H_CONFIG_CSM) == 0) { + reg |= SDMA_H_CONFIG_CSM; + writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); + } return ret; } @@ -1840,6 +1845,9 @@ static int sdma_init(struct sdma_engine *sdma) if (ret) goto disable_clk_ipg; + if (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)) + sdma->clk_ratio = 1; + /* Be sure SDMA has not started yet */ writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); @@ -1880,8 +1888,10 @@ static int sdma_init(struct sdma_engine *sdma) writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); /* Set bits of CONFIG register but with static context switching */ - /* FIXME: Check whether to set ACR bit depending on clock ratios */ - writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); + if (sdma->clk_ratio) + writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); + else + writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);