| Message ID | 20190128194343.13713-1-ccaione@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mq: Add on-chip OTP controller node | expand |
Am Montag, den 28.01.2019, 19:43 +0000 schrieb Carlo Caione: > Add the node for the OTP controller. The IP is the same as on the imx7d. > > > Signed-off-by: Carlo Caione <ccaione@baylibre.com> > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 892063a7c26c..9a5205f08f3a 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -234,6 +234,14 @@ > > reg = <0x30340000 0x10000>; > > }; > > > > + ocotp: ocotp-ctrl@30350000 { > + compatible = "fsl,imx7d-ocotp", "syscon"; Please add a imx8mq compatible here. Regards, Lucas > + reg = <0x30350000 0x10000>; > > + clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + }; > + > > > anatop: syscon@30360000 { > > compatible = "fsl,imx8mq-anatop", "syscon"; > > reg = <0x30360000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 892063a7c26c..9a5205f08f3a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -234,6 +234,14 @@ reg = <0x30340000 0x10000>; }; + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx7d-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; + #address-cells = <1>; + #size-cells = <1>; + }; + anatop: syscon@30360000 { compatible = "fsl,imx8mq-anatop", "syscon"; reg = <0x30360000 0x10000>;
Add the node for the OTP controller. The IP is the same as on the imx7d. Signed-off-by: Carlo Caione <ccaione@baylibre.com> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)