diff mbox series

[v3,1/3] arm64: dts: imx8mq: Add QuadSPI controller

Message ID 20190130120511.11555-2-ccaione@baylibre.com (mailing list archive)
State New, archived
Headers show
Series imx8mq: Add QuadSPI controller | expand

Commit Message

Carlo Caione Jan. 30, 2019, 12:05 p.m. UTC 
Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3
memory range to accommodate the QuadSPI-memory region.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

Comments

Fabio Estevam Jan. 30, 2019, 7:24 p.m. UTC | #1 
On Wed, Jan 30, 2019 at 10:05 AM Carlo Caione <ccaione@baylibre.com> wrote:
>
> Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3
> memory range to accommodate the QuadSPI-memory region.
>
> Signed-off-by: Carlo Caione <ccaione@baylibre.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Shawn Guo Feb. 11, 2019, 1:57 a.m. UTC | #2 
On Wed, Jan 30, 2019 at 12:05:09PM +0000, Carlo Caione wrote:
> Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3
> memory range to accommodate the QuadSPI-memory region.
> 
> Signed-off-by: Carlo Caione <ccaione@baylibre.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

Applied, thanks.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index dbedc4a5e7fb..2be302cb2f1f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -379,7 +379,8 @@ 
 			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x30800000 0x30800000 0x400000>;
+			ranges = <0x30800000 0x30800000 0x400000>,
+				 <0x08000000 0x08000000 0x10000000>;
 
 			uart1: serial@30860000 {
 				compatible = "fsl,imx8mq-uart",
@@ -497,6 +498,20 @@ 
 				status = "disabled";
 			};
 
+			qspi0: spi@30bb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
+				reg = <0x30bb0000 0x10000>,
+				      <0x08000000 0x10000000>;
+				reg-names = "QuadSPI", "QuadSPI-memory";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
+					 <&clk IMX8MQ_CLK_QSPI_ROOT>;
+				clock-names = "qspi_en", "qspi";
+				status = "disabled";
+			};
+
 			fec1: ethernet@30be0000 {
 				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 				reg = <0x30be0000 0x10000>;