From patchwork Thu Jan 31 09:24:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10790173 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93AFB6C2 for ; Thu, 31 Jan 2019 09:24:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9007426E3E for ; Thu, 31 Jan 2019 09:24:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7C4582FBF0; Thu, 31 Jan 2019 09:24:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 02AE626E3E for ; Thu, 31 Jan 2019 09:24:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=758PcEMR+6eU+8rzjkoDyptZatf4ugCQIRq9+CTZ/G0=; b=M1USBIq2bkTU3Z 1fZESwji00OQmxVlkN2rl6Cf0701AI/FWgpx1dH18JqJ9pJH0FAuSmhfZ0pkQr7eix+FJ0chUIjme 5N7DeWb8B14Z3CrWz4XesRYGMBeFkFdA4SXI1c5/80rEemu+W10hrq6CVm5kF3kLYwffIQq30mkmC VpkUbOtSce7z2KwoZf3624h6Y2Gqb9Yp83rds7nGjJ1OV0bzCui6iHm+OcQUkj5dwst+JvTI/kbVs nyF2I/zrRC7bhYzux/4FH+Z417tagDuSGwCjLE4nTEBDK0GI/B+klFpNdZhtMvHhuNYrfQNOge2k9 LPVhUEHuFVFdxunH7UYg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gp8aN-0004p8-Vo; Thu, 31 Jan 2019 09:24:39 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gp8a3-0004Xw-Nz for linux-arm-kernel@lists.infradead.org; Thu, 31 Jan 2019 09:24:25 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 01:24:21 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 01:24:19 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 31 Jan 2019 01:24:19 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 31 Jan 2019 09:24:18 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 31 Jan 2019 09:24:19 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 31 Jan 2019 09:24:18 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 01:24:18 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH V4 1/7] dt-bindings: timer: add Tegra210 timer Date: Thu, 31 Jan 2019 17:24:04 +0800 Message-ID: <20190131092410.28222-2-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190131092410.28222-1-josephl@nvidia.com> References: <20190131092410.28222-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548926661; bh=AtUj36W3zYQHBmv+noQJcmd4x5qNY3mVboxC574zoyc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=eQlH0d45d7dFMrSrkIfyyJMxN4L0sqxMoQG6cGpNq0LMUZL7DoGTJaQVCvbgUfCiH 8fcbQlQ2/dQFYKcCzClaq/++HzOBVtuKV+k6XOzsoS+m1NXeE/zlGI8YfckhWizCHg rCFperZMi9qRdmvV6dAVDCI2bL/dDgYdYfzKs7UHLLVTJ1MaKdDa2T5XTcneFy3vTB yNox2a4fMLLrbOC+1WOsEl5RhNvMIQx3LAxvKSx6IZr2qcG4H4wQn5n8aXG2EjgpcB T35aiZ9BRlz3rmPGKgUWsXBPYlPbZI0V/dRaCKZ1k4FhszngPpaTPiCF6U3nQSyNc1 b9XgVtTnjvkpQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190131_012420_008969_596E8B66 X-CRM114-Status: UNSURE ( 8.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , Daniel Lezcano , linux-kernel@vger.kernel.org, Joseph Lo , linux-tegra@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, or watchdog interrupts. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Reviewed-by: Rob Herring --- V4: * no change v3: * no change v2: * list all the interrupts that are supported by tegra210 timers block * add RB tag from Rob. --- .../bindings/timer/nvidia,tegra210-timer.txt | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt new file mode 100644 index 000000000000..032cda96fe0d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt @@ -0,0 +1,36 @@ +NVIDIA Tegra210 timer + +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, +or watchdog interrupts. + +Required properties: +- compatible : "nvidia,tegra210-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 14 interrupts; one per each timer channels 0 through + 13. +- clocks : Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; +};