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Thu, 31 Jan 2019 05:40:00 -0800 (PST) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 16/35] ARM: davinci: aintc: move timer-specific irq_set_handler() out of irq.c Date: Thu, 31 Jan 2019 14:39:09 +0100 Message-Id: <20190131133928.17985-17-brgl@bgdev.pl> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190131133928.17985-1-brgl@bgdev.pl> References: <20190131133928.17985-1-brgl@bgdev.pl> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190131_054004_031490_3337C2D4 X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bartosz Golaszewski I've been unable to figure out exactly why, but it seems that the IRQ_TINT1_TINT34 interrupt for timer 1 needs to be handled as a level irq, not edge like all others. This timer is used by the dsp on dm64* boards only. Let's move the handler setup out of the aintc driver where it's lived since the beginning and into the dm64* SoC-specific files where it belongs. Signed-off-by: Bartosz Golaszewski --- arch/arm/mach-davinci/dm644x.c | 4 ++++ arch/arm/mach-davinci/dm646x.c | 4 ++++ arch/arm/mach-davinci/irq.c | 1 - 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 24ad7a09aa15..beb97101c881 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -616,6 +617,9 @@ void __init dm644x_init_time(void) void __iomem *pll1, *psc; struct clk *clk; + /* Needed by the dsp. */ + irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ); pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index ab02cc93813a..70505c92d5fb 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -599,6 +600,9 @@ void __init dm646x_init_time(unsigned long ref_clk_rate, void __iomem *pll1, *psc; struct clk *clk; + /* Needed by the dsp. */ + irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index d67f443a471d..2e114ad83adc 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -142,6 +142,5 @@ void __init davinci_aintc_init(const struct davinci_aintc_config *config) davinci_aintc_setup_gc(davinci_aintc_base + reg_off, irq_base + irq_off, 32); - irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); set_handle_irq(davinci_aintc_handle_irq); }