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Tue, 5 Feb 2019 10:14:41 +0000 From: Pankaj Bansal To: Leo Li , Rob Herring , Mark Rutland Subject: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage Thread-Topic: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage Thread-Index: AQHUvTubgJLDSKArS0iRP7YRYODBng== Date: Tue, 5 Feb 2019 10:14:40 +0000 Message-ID: <20190205153924.7204-2-pankaj.bansal@nxp.com> References: <20190205153924.7204-1-pankaj.bansal@nxp.com> In-Reply-To: <20190205153924.7204-1-pankaj.bansal@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BMXPR01CA0019.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::29) To VI1PR0401MB2496.eurprd04.prod.outlook.com (2603:10a6:800:56::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pankaj.bansal@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [92.120.1.69] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; VI1PR0401MB2030; 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A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 7yvEOBh9QCi3nWo69VZKn7pQkYO3rW7SdC54hELr4CL00yqz9tGkuyDulGS9c61N9vUqEEjSPfdH6iTIdscStsX3ddvDkMK3s5C8x1pN/umpCJ61lfhj7fjcEh+hl/377RIdibeXLiwJdFj6dyeobKTeQeIy4cN/CtGyJqmDX0P44/fVCFivhlCCgEvLyX6lDsWPHtaOgalSSZnfp+eTn7RJBm41ko+ruh6kd/RF5le73Pcpl+Y9iVw0Ezmft5kubBZgs44mJbVbEkQn5au6pDhTppgyflIAVlOxt3a/gwEdo2ikJyznivuDIjLhLTweRG/KmdYPcv8MTWEtlLG21Dgbslm+9vGflBq2NJuOyCku555CWPU+pSQcQD87AOYxeMoCmzdBqVgXegSJm/OLqCawRfx+iPpCmbKCgLXZWAQ= Content-ID: <31172365421942458B85A799827935AC@eurprd04.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4abe4320-32ed-40cc-4051-08d68b52bdc9 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Feb 2019 10:14:39.3594 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2030 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190205_021447_356405_825AF265 X-CRM114-Status: GOOD ( 13.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list : OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Pankaj Bansal , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP an FPGA-based system controller, called “Qixis”, which manages several critical system features, including: • Reset sequencing • Power supply configuration • Board configuration • hardware configuration The qixis registers are accessible over one or more system-specific interfaces, typically I2C, JTAG or an embedded processor. Signed-off-by: Pankaj Bansal --- Notes: V4: - No Change V3: - Added boardname based compatible field in bindings - Added bindings for MMIO based FPGA V2: - No change .../bindings/soc/fsl/qixis_ctrl.txt | 53 ++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt new file mode 100644 index 000000000000..5d510df14be8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt @@ -0,0 +1,53 @@ +* QIXIS FPGA block + +an FPGA-based system controller, called “Qixis”, which +manages several critical system features, including: +• Configuration switch monitoring +• Power on/off sequencing +• Reset sequencing +• Power supply configuration +• Board configuration +• hardware configuration +• Background power data collection (DCM) +• Fault monitoring +• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only) +• Dedicated functional validation blocks (POSt/IRS, triggered event, and so on) +• I2C master for remote board control even with no DUT available + +The qixis registers are accessible over one or more system-specific interfaces, +typically I2C, JTAG or an embedded processor. + +FPGA connected to I2C: +Required properties: + + - compatible: should be a board-specific string followed by a string + indicating the type of FPGA. Example: + "fsl,-fpga", "fsl,fpga-qixis-i2c" + - reg : i2c address of the qixis device. + +Example (LX2160A-QDS): + /* The FPGA node */ + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c"; + reg = <0x66>; + #address-cells = <1>; + #size-cells = <0>; + } + +* Freescale on-board FPGA + +This is the memory-mapped registers for on board FPGA. + +Required properties: +- compatible: should be a board-specific string followed by a string + indicating the type of FPGA. Example: + "fsl,-fpga", "fsl,fpga-qixis" +- reg: should contain the address and the length of the FPGA register set. + +Example (LS2080A-RDB): + + cpld@3,0 { + compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis"; + reg = <0x3 0 0x10000>; + }; +