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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id v22sm11061612wml.37.2019.02.07.05.26.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 05:26:25 -0800 (PST) From: Jerome Brunet To: Kevin Hilman Subject: [PATCH 2/2] soc: amlogic: clk-measure: fix-up some clock definitions Date: Thu, 7 Feb 2019 14:26:03 +0100 Message-Id: <20190207132603.694-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190207132603.694-1-jbrunet@baylibre.com> References: <20190207132603.694-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190207_052627_673047_A6FF4B03 X-CRM114-Status: GOOD ( 11.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP As pointed out in review, a few clock are not properly defined. Reported-by: Martin Blumenstingl Fixes: 2a4c63e080cd ("soc: amlogic: clk-measure: add axg and g12a support") Signed-off-by: Jerome Brunet --- drivers/soc/amlogic/meson-clk-measure.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index 5570180b94a1..19d4cbc93a17 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -202,7 +202,7 @@ static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { CLK_MSR_ID(71, "audio_slv_sclk_a"), CLK_MSR_ID(72, "pwm_d"), CLK_MSR_ID(73, "pwm_c"), - CLK_MSR_ID(73, "wifi_beacon"), + CLK_MSR_ID(74, "wifi_beacon"), CLK_MSR_ID(75, "tdmin_lb_lrcl"), CLK_MSR_ID(76, "tdmin_lb_sclk"), CLK_MSR_ID(77, "rng_ring_osc_0"), @@ -268,6 +268,8 @@ static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { CLK_MSR_ID(26, "sc_int"), CLK_MSR_ID(27, "in_mac"), CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(29, "pcie_inp"), + CLK_MSR_ID(30, "pcie_inn"), CLK_MSR_ID(31, "mpll_test_out"), CLK_MSR_ID(32, "vdec"), CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), @@ -303,8 +305,8 @@ static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { CLK_MSR_ID(65, "spicc_0"), CLK_MSR_ID(66, "vid_lock"), CLK_MSR_ID(67, "dsi_phy"), - CLK_MSR_ID(68, "hdcp22_skp"), - CLK_MSR_ID(69, "hdcp22_esm"), + CLK_MSR_ID(68, "hdcp22_esm"), + CLK_MSR_ID(69, "hdcp22_skp"), CLK_MSR_ID(70, "pwm_f"), CLK_MSR_ID(71, "pwm_e"), CLK_MSR_ID(72, "pwm_d"),