| Message ID | 20190211071555.31430-2-seiya.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1,1/2] arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72 | expand |
On 11/02/2019 08:15, Seiya Wang wrote: > Change cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/mediatek/clk-mt8173.c | 4 ++-- > include/dt-bindings/clock/mt8173-clk.h | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c > index 96c292c3e440..deedeb3ea33b 100644 > --- a/drivers/clk/mediatek/clk-mt8173.c > +++ b/drivers/clk/mediatek/clk-mt8173.c > @@ -533,7 +533,7 @@ static const char * const ca53_parents[] __initconst = { > "univpll" > }; > > -static const char * const ca57_parents[] __initconst = { > +static const char * const ca72_parents[] __initconst = { > "clk26m", > "armca15pll", > "mainpll", > @@ -542,7 +542,7 @@ static const char * const ca57_parents[] __initconst = { > > static const struct mtk_composite cpu_muxes[] __initconst = { > MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), > - MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2), > + MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), > }; > > static const struct mtk_composite top_muxes[] __initconst = { > diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h > index 8aea623dd518..f7e5356fd602 100644 > --- a/include/dt-bindings/clock/mt8173-clk.h > +++ b/include/dt-bindings/clock/mt8173-clk.h > @@ -194,7 +194,7 @@ > #define CLK_INFRA_PMICWRAP 11 > #define CLK_INFRA_CLK_13M 12 > #define CLK_INFRA_CA53SEL 13 > -#define CLK_INFRA_CA57SEL 14 > +#define CLK_INFRA_CA72SEL 14 > #define CLK_INFRA_NR_CLK 15 > > /* PERI_SYS */ >
Quoting Seiya Wang (2019-02-10 23:15:55) > Change cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> I'm guessing I can't apply this patch because the define is renamed which would break older DTs. Another option would be to just add another define and mark the old define as deprecated and unsupported. Then I could apply the patch to clk tree.
On Thu, 2019-02-21 at 14:03 -0800, Stephen Boyd wrote: > Quoting Seiya Wang (2019-02-10 23:15:55) > > Change cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. > > > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> > > --- > > Acked-by: Stephen Boyd <sboyd@kernel.org> > > I'm guessing I can't apply this patch because the define is renamed > which would break older DTs. Another option would be to just add another > define and mark the old define as deprecated and unsupported. Then I > could apply the patch to clk tree. Thank you so much for your advice. We will update the patches and resend soon.
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 96c292c3e440..deedeb3ea33b 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -533,7 +533,7 @@ static const char * const ca53_parents[] __initconst = { "univpll" }; -static const char * const ca57_parents[] __initconst = { +static const char * const ca72_parents[] __initconst = { "clk26m", "armca15pll", "mainpll", @@ -542,7 +542,7 @@ static const char * const ca57_parents[] __initconst = { static const struct mtk_composite cpu_muxes[] __initconst = { MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), - MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2), + MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), }; static const struct mtk_composite top_muxes[] __initconst = { diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 8aea623dd518..f7e5356fd602 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -194,7 +194,7 @@ #define CLK_INFRA_PMICWRAP 11 #define CLK_INFRA_CLK_13M 12 #define CLK_INFRA_CA53SEL 13 -#define CLK_INFRA_CA57SEL 14 +#define CLK_INFRA_CA72SEL 14 #define CLK_INFRA_NR_CLK 15 /* PERI_SYS */
Change cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> --- drivers/clk/mediatek/clk-mt8173.c | 4 ++-- include/dt-bindings/clock/mt8173-clk.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)