| Message ID | 20190211161736.23844-1-nava.manne@xilinx.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Bitstream configuration support for ZynqMP | expand |
Hi Nava, a couple of nits inline. otherwise looks fine to me. On Sun, Feb 10, 2019 at 8:17 AM Nava kishore Manne <nava.manne@xilinx.com> wrote: > > Add documentation to describe Xilinx ZynqMP fpga driver > bindings. > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > --- > Changes for v3: > -Created patches on top of 5.0-rc5. > No functional changes. > Changes for v2: > -Removed "----" separators. > Changes for v1: > -Created a Seperate(New) DT binding file as > suggested by Rob. > > Changes for RFC-V2: > -Moved pcap node as a child to firwmare > node as suggested by Rob. > > .../devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > new file mode 100644 > index 0000000..1f6f588 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > @@ -0,0 +1,13 @@ > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled > +using ZynqMP SoC firmware interface How about: Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager. > +For Bitstream configuration on ZynqMp Soc uses processor configuration > +port(PCAP) to configure the programmable logic(PL) through PS by using > +FW interface. ZynqMP or ZynqMp, let's stay consistent here. How about: The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the Programmable Logic (PL). The configuration uses the firmware interface. > + > +Required properties: > +- compatible: should contain "xlnx,zynqmp-pcap-fpga" > + > +Example: > + zynqmp_pcap: pcap { > + compatible = "xlnx,zynqmp-pcap-fpga"; > + }; > -- > 2.7.4 > Thanks, Moritz
On Mon, Feb 11, 2019 at 09:47:36PM +0530, Nava kishore Manne wrote: > Add documentation to describe Xilinx ZynqMP fpga driver > bindings. I thought I was told in the review of the firmware binding that is went away... > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > --- > Changes for v3: > -Created patches on top of 5.0-rc5. > No functional changes. > Changes for v2: > -Removed "----" separators. > Changes for v1: > -Created a Seperate(New) DT binding file as > suggested by Rob. > > Changes for RFC-V2: > -Moved pcap node as a child to firwmare > node as suggested by Rob. > > .../devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > new file mode 100644 > index 0000000..1f6f588 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > @@ -0,0 +1,13 @@ > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled > +using ZynqMP SoC firmware interface > +For Bitstream configuration on ZynqMp Soc uses processor configuration > +port(PCAP) to configure the programmable logic(PL) through PS by using > +FW interface. > + > +Required properties: > +- compatible: should contain "xlnx,zynqmp-pcap-fpga" > + > +Example: > + zynqmp_pcap: pcap { > + compatible = "xlnx,zynqmp-pcap-fpga"; There's no DT resources here, so there's no need for this in DT. Just have the parent (the firmware driver) instantiate the driver. Rob
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt new file mode 100644 index 0000000..1f6f588 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt @@ -0,0 +1,13 @@ +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled +using ZynqMP SoC firmware interface +For Bitstream configuration on ZynqMp Soc uses processor configuration +port(PCAP) to configure the programmable logic(PL) through PS by using +FW interface. + +Required properties: +- compatible: should contain "xlnx,zynqmp-pcap-fpga" + +Example: + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + };
Add documentation to describe Xilinx ZynqMP fpga driver bindings. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> --- Changes for v3: -Created patches on top of 5.0-rc5. No functional changes. Changes for v2: -Removed "----" separators. Changes for v1: -Created a Seperate(New) DT binding file as suggested by Rob. Changes for RFC-V2: -Moved pcap node as a child to firwmare node as suggested by Rob. .../devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt