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[90.86.93.32]) by smtp.gmail.com with ESMTPSA id c14sm3708656wrn.12.2019.02.12.02.39.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Feb 2019 02:39:11 -0800 (PST) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier , David Lechner Subject: [PATCH v3 13/37] ARM: davinci: aintc: drop the 00 prefix from register offsets Date: Tue, 12 Feb 2019 11:38:11 +0100 Message-Id: <20190212103835.7768-14-brgl@bgdev.pl> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190212103835.7768-1-brgl@bgdev.pl> References: <20190212103835.7768-1-brgl@bgdev.pl> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190212_023914_390811_C1D58BD3 X-CRM114-Status: GOOD ( 11.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bartosz Golaszewski Since no offset goes past 0xff - let's drop the 00 prefix for better readability. While we're at it: convert all hex numbers to lower-case. Signed-off-by: Bartosz Golaszewski Reviewed-by: David Lechner --- arch/arm/mach-davinci/irq.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 2eb3d9b9f65f..2df91fc0dade 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -19,17 +19,17 @@ #include "irqs.h" -#define DAVINCI_AINTC_FIQ_REG0 0x0000 -#define DAVINCI_AINTC_FIQ_REG1 0x0004 -#define DAVINCI_AINTC_IRQ_REG0 0x0008 -#define DAVINCI_AINTC_IRQ_REG1 0x000C -#define DAVINCI_AINTC_IRQ_IRQENTRY 0x0014 -#define DAVINCI_AINTC_IRQ_ENT_REG0 0x0018 -#define DAVINCI_AINTC_IRQ_ENT_REG1 0x001C -#define DAVINCI_AINTC_IRQ_INCTL_REG 0x0020 -#define DAVINCI_AINTC_IRQ_EABASE_REG 0x0024 -#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x0030 -#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x004C +#define DAVINCI_AINTC_FIQ_REG0 0x00 +#define DAVINCI_AINTC_FIQ_REG1 0x04 +#define DAVINCI_AINTC_IRQ_REG0 0x08 +#define DAVINCI_AINTC_IRQ_REG1 0x0c +#define DAVINCI_AINTC_IRQ_IRQENTRY 0x14 +#define DAVINCI_AINTC_IRQ_ENT_REG0 0x18 +#define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c +#define DAVINCI_AINTC_IRQ_INCTL_REG 0x20 +#define DAVINCI_AINTC_IRQ_EABASE_REG 0x24 +#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30 +#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c static void __iomem *davinci_aintc_base; static struct irq_domain *davinci_aintc_irq_domain;