Message ID | 20190226070742.30551-2-daniel.baluta@nxp.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Tue, 26 Feb 2019 07:08:12 +0000 From: Daniel Baluta <daniel.baluta@nxp.com> To: "shawnguo@kernel.org" <shawnguo@kernel.org> Subject: [PATCH v3 1/5] arm64: dts: imx8mq: Add SDMA nodes Thread-Topic: [PATCH v3 1/5] arm64: dts: imx8mq: Add SDMA nodes Thread-Index: AQHUzaIJaz1vuE2TVUKFPBLSrvtSQQ== Date: Tue, 26 Feb 2019 07:08:12 +0000 Message-ID: <20190226070742.30551-2-daniel.baluta@nxp.com> References: <20190226070742.30551-1-daniel.baluta@nxp.com> In-Reply-To: <20190226070742.30551-1-daniel.baluta@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR04CA0102.eurprd04.prod.outlook.com (2603:10a6:803:64::37) To VI1PR0402MB3357.eurprd04.prod.outlook.com (2603:10a6:803:2::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=daniel.baluta@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [95.76.156.53] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a4922cb2-9cfe-495f-eb51-08d69bb92b77 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Series | Enable wm8524 on i.MX8MQ | expand |
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9155bd4784eb..8cafec17726b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -234,6 +234,17 @@ status = "disabled"; }; + sdma2: sdma@302c0000 { + compatible = "fsl,imx7d-sdma"; + reg = <0x302c0000 0x10000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, + <&clk IMX8MQ_CLK_SDMA2_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x30330000 0x10000>; @@ -575,6 +586,17 @@ status = "disabled"; }; + sdma1: sdma@30bd0000 { + compatible = "fsl,imx7d-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, + <&clk IMX8MQ_CLK_SDMA1_ROOT>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + fec1: ethernet@30be0000 { compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>;