| Message ID | 20190227010544.597579-8-jeremy.linton@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: add system vulnerability sysfs entries | expand |
Hi, On 2/26/19 7:05 PM, Jeremy Linton wrote: > Add code to track whether all the cores in the machine are > vulnerable, and whether all the vulnerable cores have been > mitigated. > > Once we have that information we can add the sysfs stub and > provide an accurate view of what is known about the machine. > > Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> > --- > arch/arm64/kernel/cpu_errata.c | 28 +++++++++++++++++++++++++++- > 1 file changed, 27 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index a27e1ee750e1..0f6e8f5d67bc 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -513,6 +513,10 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) > .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ > CAP_MIDR_RANGE_LIST(midr_list) > > +/* Track overall mitigation state. We are only mitigated if all cores are ok */ > +static bool __hardenbp_enab = true; > +static bool __spectrev2_safe = true; > + > /* > * List of CPUs that do not need any Spectre-v2 mitigation at all. > */ > @@ -523,6 +527,10 @@ static const struct midr_range spectre_v2_safe_list[] = { > { /* sentinel */ } > }; > > +/* > + * Track overall bp hardening for all heterogeneous cores in the machine. > + * We are only considered "safe" if all booted cores are known safe. > + */ > static bool __maybe_unused > check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) > { > @@ -544,19 +552,25 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) > if (!need_wa) > return false; > > + __spectrev2_safe = false; > + > if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) { > pr_warn_once("spectrev2 mitigation disabled by configuration\n"); > + __hardenbp_enab = false; > return false; > } > > /* forced off */ > if (__nospectre_v2) { > pr_info_once("spectrev2 mitigation disabled by command line option\n"); > + __hardenbp_enab = false; > return false; > } > > - if (need_wa < 0) > + if (need_wa < 0) { > pr_warn_once("ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware\n"); > + __hardenbp_enab = false; > + } > > return (need_wa > 0); > } > @@ -779,3 +793,15 @@ ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, > { > return sprintf(buf, "Mitigation: __user pointer sanitization\n"); > } > + > +ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, > + char *buf) w/s issue Anyway: Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre. > +{ > + if (__spectrev2_safe) > + return sprintf(buf, "Not affected\n"); > + > + if (__hardenbp_enab) > + return sprintf(buf, "Mitigation: Branch predictor hardening\n"); > + > + return sprintf(buf, "Vulnerable\n"); > +} >
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a27e1ee750e1..0f6e8f5d67bc 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -513,6 +513,10 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ CAP_MIDR_RANGE_LIST(midr_list) +/* Track overall mitigation state. We are only mitigated if all cores are ok */ +static bool __hardenbp_enab = true; +static bool __spectrev2_safe = true; + /* * List of CPUs that do not need any Spectre-v2 mitigation at all. */ @@ -523,6 +527,10 @@ static const struct midr_range spectre_v2_safe_list[] = { { /* sentinel */ } }; +/* + * Track overall bp hardening for all heterogeneous cores in the machine. + * We are only considered "safe" if all booted cores are known safe. + */ static bool __maybe_unused check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) { @@ -544,19 +552,25 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) if (!need_wa) return false; + __spectrev2_safe = false; + if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) { pr_warn_once("spectrev2 mitigation disabled by configuration\n"); + __hardenbp_enab = false; return false; } /* forced off */ if (__nospectre_v2) { pr_info_once("spectrev2 mitigation disabled by command line option\n"); + __hardenbp_enab = false; return false; } - if (need_wa < 0) + if (need_wa < 0) { pr_warn_once("ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware\n"); + __hardenbp_enab = false; + } return (need_wa > 0); } @@ -779,3 +793,15 @@ ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, { return sprintf(buf, "Mitigation: __user pointer sanitization\n"); } + +ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, + char *buf) +{ + if (__spectrev2_safe) + return sprintf(buf, "Not affected\n"); + + if (__hardenbp_enab) + return sprintf(buf, "Mitigation: Branch predictor hardening\n"); + + return sprintf(buf, "Vulnerable\n"); +}
Add code to track whether all the cores in the machine are vulnerable, and whether all the vulnerable cores have been mitigated. Once we have that information we can add the sysfs stub and provide an accurate view of what is known about the machine. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> --- arch/arm64/kernel/cpu_errata.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-)