| Message ID | 20190307151342.7381-7-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: g12a: Add peripherals | expand |
Neil Armstrong <narmstrong@baylibre.com> writes: > This patch adds the 2 UART nodes in the EE power domain with the corresponding > pinctrl nodes. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Similar to PATCH 4/9, are you wanting to move this to the board series? Kevin > --- > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++ > 1 file changed, 82 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > index 2a700bb45d04..50e2cd36e08b 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > @@ -113,6 +113,61 @@ > #gpio-cells = <2>; > gpio-ranges = <&periphs_pinctrl 0 0 86>; > }; > + > + uart_a_pins: uart_a { > + mux { > + groups = "uart_a_tx", > + "uart_a_rx"; > + function = "uart_a"; > + bias-disable; > + }; > + }; > + > + uart_a_cts_rts_pins: uart_a_cts_rts { > + mux { > + groups = "uart_a_cts", > + "uart_a_rts"; > + function = "uart_a"; > + bias-disable; > + }; > + }; > + > + uart_ao_a_c_pins: uart_ao_a_c { > + mux { > + groups = "uart_ao_a_rx_c", > + "uart_ao_a_tx_c"; > + function = "uart_ao_a_c"; > + bias-disable; > + }; > + }; > + > + uart_b_pins: uart_b { > + mux { > + groups = "uart_b_tx", > + "uart_b_rx"; > + function = "uart_b"; > + bias-disable; > + }; > + }; > + > + uart_c_pins: uart_c { > + mux { > + groups = "uart_c_tx", > + "uart_c_rx"; > + function = "uart_c"; > + bias-disable; > + }; > + }; > + > + uart_c_cts_rts_pins: uart_c_cts_rts { > + mux { > + groups = "uart_c_cts", > + "uart_c_rts"; > + function = "uart_c"; > + bias-disable; > + }; > + }; > + }; > }; > > hiu: bus@3c000 { > @@ -256,6 +311,33 @@ > compatible = "amlogic,meson-g12a-clk-measure"; > reg = <0x0 0x18000 0x0 0x10>; > }; > + > + uart_C: serial@22000 { > + compatible = "amlogic,meson-gx-uart"; > + reg = <0x0 0x22000 0x0 0x18>; > + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; > + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; > + clock-names = "xtal", "pclk", "baud"; > + status = "disabled"; > + }; > + > + uart_B: serial@23000 { > + compatible = "amlogic,meson-gx-uart"; > + reg = <0x0 0x23000 0x0 0x18>; > + interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; > + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; > + clock-names = "xtal", "pclk", "baud"; > + status = "disabled"; > + }; > + > + uart_A: serial@24000 { > + compatible = "amlogic,meson-gx-uart"; > + reg = <0x0 0x24000 0x0 0x18>; > + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; > + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; > + clock-names = "xtal", "pclk", "baud"; > + status = "disabled"; > + }; > }; > }; > > -- > 2.20.1
Hi Neil, On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong <narmstrong@baylibre.com> wrote: > > This patch adds the 2 UART nodes in the EE power domain with the corresponding > pinctrl nodes. there are 3 UART controllers in the EE power domain > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++ > 1 file changed, 82 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > index 2a700bb45d04..50e2cd36e08b 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > @@ -113,6 +113,61 @@ > #gpio-cells = <2>; > gpio-ranges = <&periphs_pinctrl 0 0 86>; > }; > + > + uart_a_pins: uart_a { (this applies to all new nodes) we started using dashes for the node names for new pin definitions on the GX SoCs. I don't remember where it was discussed exactly but I think this was requested from Rob since G12A is a new SoC we should do it "right" from the beginning [...] > + uart_ao_a_c_pins: uart_ao_a_c { > + mux { > + groups = "uart_ao_a_rx_c", > + "uart_ao_a_tx_c"; > + function = "uart_ao_a_c"; > + bias-disable; > + }; > + }; I'm fine with this part if you mention it in the subject and/or the description uart_ao_a_c routes two pins from bank C (from the EE domain) to the uart_AO controller (from the AO domain) > + uart_b_pins: uart_b { > + mux { > + groups = "uart_b_tx", > + "uart_b_rx"; > + function = "uart_b"; > + bias-disable; > + }; > + }; > + > + uart_c_pins: uart_c { > + mux { > + groups = "uart_c_tx", > + "uart_c_rx"; > + function = "uart_c"; > + bias-disable; > + }; > + }; > + > + uart_c_cts_rts_pins: uart_c_cts_rts { > + mux { > + groups = "uart_c_cts", > + "uart_c_rts"; > + function = "uart_c"; > + bias-disable; > + }; > + }; > + }; > }; > > hiu: bus@3c000 { > @@ -256,6 +311,33 @@ > compatible = "amlogic,meson-g12a-clk-measure"; > reg = <0x0 0x18000 0x0 0x10>; > }; > + > + uart_C: serial@22000 { > + compatible = "amlogic,meson-gx-uart"; > + reg = <0x0 0x22000 0x0 0x18>; > + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; > + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2 Regards Martin
Le 15/03/2019 22:24, Martin Blumenstingl a écrit : > Hi Neil, > > On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong <narmstrong@baylibre.com> wrote: >> >> This patch adds the 2 UART nodes in the EE power domain with the corresponding >> pinctrl nodes. > there are 3 UART controllers in the EE power domain Good catch ! > >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> --- >> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++ >> 1 file changed, 82 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> index 2a700bb45d04..50e2cd36e08b 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> @@ -113,6 +113,61 @@ >> #gpio-cells = <2>; >> gpio-ranges = <&periphs_pinctrl 0 0 86>; >> }; >> + >> + uart_a_pins: uart_a { > (this applies to all new nodes) > we started using dashes for the node names for new pin definitions on > the GX SoCs. > I don't remember where it was discussed exactly but I think this was > requested from Rob Yes I remember, will fix > > since G12A is a new SoC we should do it "right" from the beginning > > [...] >> + uart_ao_a_c_pins: uart_ao_a_c { >> + mux { >> + groups = "uart_ao_a_rx_c", >> + "uart_ao_a_tx_c"; >> + function = "uart_ao_a_c"; >> + bias-disable; >> + }; >> + }; > I'm fine with this part if you mention it in the subject and/or the description > uart_ao_a_c routes two pins from bank C (from the EE domain) to the > uart_AO controller (from the AO domain) Not sure DT is the right place for that, I think I'll remove this until we have it actually used somewhere. > >> + uart_b_pins: uart_b { >> + mux { >> + groups = "uart_b_tx", >> + "uart_b_rx"; >> + function = "uart_b"; >> + bias-disable; >> + }; >> + }; >> + >> + uart_c_pins: uart_c { >> + mux { >> + groups = "uart_c_tx", >> + "uart_c_rx"; >> + function = "uart_c"; >> + bias-disable; >> + }; >> + }; >> + >> + uart_c_cts_rts_pins: uart_c_cts_rts { >> + mux { >> + groups = "uart_c_cts", >> + "uart_c_rts"; >> + function = "uart_c"; >> + bias-disable; >> + }; >> + }; >> + }; >> }; >> >> hiu: bus@3c000 { >> @@ -256,6 +311,33 @@ >> compatible = "amlogic,meson-g12a-clk-measure"; >> reg = <0x0 0x18000 0x0 0x10>; >> }; >> + >> + uart_C: serial@22000 { >> + compatible = "amlogic,meson-gx-uart"; >> + reg = <0x0 0x22000 0x0 0x18>; >> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; >> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; > does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2 It seems so : https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L1020 Neil > > > Regards > Martin >
Hi Neil, On Sat, Mar 16, 2019 at 3:35 PM Neil Armstrong <narmstrong@baylibre.com> wrote: [...] > >> + uart_ao_a_c_pins: uart_ao_a_c { > >> + mux { > >> + groups = "uart_ao_a_rx_c", > >> + "uart_ao_a_tx_c"; > >> + function = "uart_ao_a_c"; > >> + bias-disable; > >> + }; > >> + }; > > I'm fine with this part if you mention it in the subject and/or the description > > uart_ao_a_c routes two pins from bank C (from the EE domain) to the > > uart_AO controller (from the AO domain) > > Not sure DT is the right place for that, I think I'll remove this until > we have it actually used somewhere. I'm fine with that as well [...] > >> + > >> + uart_C: serial@22000 { > >> + compatible = "amlogic,meson-gx-uart"; > >> + reg = <0x0 0x22000 0x0 0x18>; > >> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; > >> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; > > does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2 > > It seems so : > https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L1020 it's weird but we can always fix it up later if needed. so let's keep it for now to stay consistent with the vendor kernel until we know better Jianxin, can you please check with the hardware team whether the uart_C gate clock (pclk) is CLKID_UART1 or CLKID_UART2 on G12A? Regards Martin
Le 16/03/2019 23:14, Martin Blumenstingl a écrit : > Hi Neil, > > On Sat, Mar 16, 2019 at 3:35 PM Neil Armstrong <narmstrong@baylibre.com> wrote: > [...] >>>> + uart_ao_a_c_pins: uart_ao_a_c { >>>> + mux { >>>> + groups = "uart_ao_a_rx_c", >>>> + "uart_ao_a_tx_c"; >>>> + function = "uart_ao_a_c"; >>>> + bias-disable; >>>> + }; >>>> + }; >>> I'm fine with this part if you mention it in the subject and/or the description >>> uart_ao_a_c routes two pins from bank C (from the EE domain) to the >>> uart_AO controller (from the AO domain) >> >> Not sure DT is the right place for that, I think I'll remove this until >> we have it actually used somewhere. > I'm fine with that as well > > [...] >>>> + >>>> + uart_C: serial@22000 { >>>> + compatible = "amlogic,meson-gx-uart"; >>>> + reg = <0x0 0x22000 0x0 0x18>; >>>> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; >>>> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; >>> does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2 >> >> It seems so : >> https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L1020 > it's weird but we can always fix it up later if needed. so let's keep > it for now to stay consistent with the vendor kernel until we know > better > > Jianxin, can you please check with the hardware team whether the > uart_C gate clock (pclk) is CLKID_UART1 or CLKID_UART2 on G12A? I think it's a typo, it should use CLKID_UART2 Neil > > > Regards > Martin >
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 2a700bb45d04..50e2cd36e08b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -113,6 +113,61 @@ #gpio-cells = <2>; gpio-ranges = <&periphs_pinctrl 0 0 86>; }; + + uart_a_pins: uart_a { + mux { + groups = "uart_a_tx", + "uart_a_rx"; + function = "uart_a"; + bias-disable; + }; + }; + + uart_a_cts_rts_pins: uart_a_cts_rts { + mux { + groups = "uart_a_cts", + "uart_a_rts"; + function = "uart_a"; + bias-disable; + }; + }; + + uart_ao_a_c_pins: uart_ao_a_c { + mux { + groups = "uart_ao_a_rx_c", + "uart_ao_a_tx_c"; + function = "uart_ao_a_c"; + bias-disable; + }; + }; + + uart_b_pins: uart_b { + mux { + groups = "uart_b_tx", + "uart_b_rx"; + function = "uart_b"; + bias-disable; + }; + }; + + uart_c_pins: uart_c { + mux { + groups = "uart_c_tx", + "uart_c_rx"; + function = "uart_c"; + bias-disable; + }; + }; + + uart_c_cts_rts_pins: uart_c_cts_rts { + mux { + groups = "uart_c_cts", + "uart_c_rts"; + function = "uart_c"; + bias-disable; + }; + }; + }; }; hiu: bus@3c000 { @@ -256,6 +311,33 @@ compatible = "amlogic,meson-g12a-clk-measure"; reg = <0x0 0x18000 0x0 0x10>; }; + + uart_C: serial@22000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_B: serial@23000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x23000 0x0 0x18>; + interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_A: serial@24000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x24000 0x0 0x18>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; }; };
This patch adds the 2 UART nodes in the EE power domain with the corresponding pinctrl nodes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++ 1 file changed, 82 insertions(+)