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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id r15sm5756563wrt.37.2019.03.07.07.13.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Mar 2019 07:13:48 -0800 (PST) From: Neil Armstrong To: khilman@baylibre.com Subject: [PATCH 6/9] arm64: dts: meson: g12a: Add UART A, B & C nodes and pins Date: Thu, 7 Mar 2019 16:13:38 +0100 Message-Id: <20190307151342.7381-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307151342.7381-1-narmstrong@baylibre.com> References: <20190307151342.7381-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190307_071350_470346_705C48B3 X-CRM114-Status: GOOD ( 11.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the 2 UART nodes in the EE power domain with the corresponding pinctrl nodes. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 2a700bb45d04..50e2cd36e08b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -113,6 +113,61 @@ #gpio-cells = <2>; gpio-ranges = <&periphs_pinctrl 0 0 86>; }; + + uart_a_pins: uart_a { + mux { + groups = "uart_a_tx", + "uart_a_rx"; + function = "uart_a"; + bias-disable; + }; + }; + + uart_a_cts_rts_pins: uart_a_cts_rts { + mux { + groups = "uart_a_cts", + "uart_a_rts"; + function = "uart_a"; + bias-disable; + }; + }; + + uart_ao_a_c_pins: uart_ao_a_c { + mux { + groups = "uart_ao_a_rx_c", + "uart_ao_a_tx_c"; + function = "uart_ao_a_c"; + bias-disable; + }; + }; + + uart_b_pins: uart_b { + mux { + groups = "uart_b_tx", + "uart_b_rx"; + function = "uart_b"; + bias-disable; + }; + }; + + uart_c_pins: uart_c { + mux { + groups = "uart_c_tx", + "uart_c_rx"; + function = "uart_c"; + bias-disable; + }; + }; + + uart_c_cts_rts_pins: uart_c_cts_rts { + mux { + groups = "uart_c_cts", + "uart_c_rts"; + function = "uart_c"; + bias-disable; + }; + }; + }; }; hiu: bus@3c000 { @@ -256,6 +311,33 @@ compatible = "amlogic,meson-g12a-clk-measure"; reg = <0x0 0x18000 0x0 0x10>; }; + + uart_C: serial@22000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_B: serial@23000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x23000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_A: serial@24000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x24000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; }; };