Message ID | 20190311093130.7209-11-Zhiqiang.Hou@nxp.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs | expand |
On Mon, Mar 11, 2019 at 09:31:16AM +0000, Z.q. Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > In the loop block, there is not code change the loop key, > this patch updated the loop key by re-read the INTx status > register. > > This patch also change to clear the handled INTx status. > > Note: Need MV to test this fix. > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host > Bridge IP driver") The "Fixes:" line should be all on one line, without a newline in the middle, even if it exceeds 80 columns. That's just to make it easier for programs to parse the logs.
Hi Bjorn, Thanks a lot for your comments! > -----Original Message----- > From: Bjorn Helgaas [mailto:helgaas@kernel.org] > Sent: 2019年3月11日 22:08 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > robh+dt@kernel.org; mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in; > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; > lorenzo.pieralisi@arm.com; catalin.marinas@arm.com; > will.deacon@arm.com; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao > <xiaowei.bao@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com> > Subject: Re: [PATCHv4 10/28] PCI: mobiveil: fix the INTx process error > > On Mon, Mar 11, 2019 at 09:31:16AM +0000, Z.q. Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > In the loop block, there is not code change the loop key, this patch > > updated the loop key by re-read the INTx status register. > > > > This patch also change to clear the handled INTx status. > > > > Note: Need MV to test this fix. > > > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP > > driver") > > The "Fixes:" line should be all on one line, without a newline in the middle, > even if it exceeds 80 columns. That's just to make it easier for programs to > parse the logs. Will fix in v5. Thanks, Zhiqiang
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 4ba458474e42..78e575e71f4d 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) /* Handle INTx */ if (intr_status & PAB_INTP_INTX_MASK) { shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); + shifted_status &= PAB_INTP_INTX_MASK; shifted_status >>= PAB_INTX_START; do { for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) { @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc) dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit); - /* clear interrupt */ - csr_writel(pcie, - shifted_status << PAB_INTX_START, + /* clear interrupt handled */ + csr_writel(pcie, 1 << (PAB_INTX_START + bit), PAB_INTP_AMBA_MISC_STAT); } - } while ((shifted_status >> PAB_INTX_START) != 0); + + shifted_status = csr_readl(pcie, + PAB_INTP_AMBA_MISC_STAT); + shifted_status &= PAB_INTP_INTX_MASK; + shifted_status >>= PAB_INTX_START; + } while (shifted_status != 0); } /* read extra MSI status register */