From patchwork Mon Apr 1 03:35:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhiyong.tao" X-Patchwork-Id: 10878993 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 275F313B5 for ; Mon, 1 Apr 2019 03:36:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0C35B28628 for ; Mon, 1 Apr 2019 03:36:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0050C287E9; Mon, 1 Apr 2019 03:36:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 586E828628 for ; Mon, 1 Apr 2019 03:36:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iUeDKiFJ0ajZwUlJ7LVnFbi84Vh0VDXT48gJzZ+jIDU=; b=GfdHc57CqTqd3N FhFa8BcIOVETGeK4JhnbcT/aNMbC+dS2vvxXZQdRj3nQp2SMYWqDsvObpigRz0+fw1mpK0Gyhre7o I+5NfDg11x6ozAF5kwGZZ7dagpzVzPKQ/TRAYULhwcJYhobmJicPR6pqC9z5A837DUOQ60OoyRhE4 O/epouELjcNWVAl3MkZXBvzD+FeIqsWuwk769gIOr94KTWH0ryTc3BQjNzBQ43ISt+lzBD/U2WaHn 80cHP9uZFKNixBa4JwGBnC8+A74qBI6ZOlosqoqltucNN/MzizmdjkfzrJB3d5tnBDao9doLp+nfI DJvt5bnCLI8VgcmP7UsQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hAnjz-0001Sb-SH; Mon, 01 Apr 2019 03:36:07 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hAnjt-0001Or-UB; Mon, 01 Apr 2019 03:36:03 +0000 X-UUID: dd8e6f2abcd44cda93da60e050d88721-20190331 X-UUID: dd8e6f2abcd44cda93da60e050d88721-20190331 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 60803698; Sun, 31 Mar 2019 19:35:51 -0800 Received: from mtkmbs03n2.mediatek.inc (172.21.101.182) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 31 Mar 2019 20:35:50 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 1 Apr 2019 11:35:45 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 1 Apr 2019 11:35:44 +0800 From: Zhiyong Tao To: , , , , Subject: [PATCH v4 4/4] pinctrl: add drive for I2C related pins on MT8183 Date: Mon, 1 Apr 2019 11:35:35 +0800 Message-ID: <20190401033535.16910-5-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20190401033535.16910-1-zhiyong.tao@mediatek.com> References: <20190401033535.16910-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: AE27C56FA0D2BCC451B5A8CAC8DCD77A62582905FF7D463E328C9C0F64F292A92000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190331_203602_050069_59EF1B8B X-CRM114-Status: GOOD ( 15.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, sean.wang@mediatek.com, srv_heupstream@mediatek.com, chuanjia.liu@mediatek.com, biao.huang@mediatek.com, zhiyong.tao@mediatek.com, erin.lo@mediatek.com, hui.liu@mediatek.com, linux-kernel@vger.kernel.org, hongzhou.yang@mediatek.com, linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch provides the advanced drive for I2C used pins on MT8183. The detail strength specification description of the I2C pin: When E1=0/E0=0, the strength is 0.125mA. When E1=0/E0=1, the strength is 0.25mA. When E1=1/E0=0, the strength is 0.5mA. When E1=1/E0=1, the strength is 1mA. For I2C pins, there are existing generic driving setup and the above specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving adjustment in generic driving setup. But in specific driving setup, they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific driving setup for I2C pins, the existing generic driving setup will be disabled. For some special features, we need the I2C pins specific driving setup. The specific driving setup is controlled by E1E0EN. So we need add extra vendor driving preperty instead of the generic driving property. We can add "mediatek,drive-strength-adv = ;" to describe the specific driving setup property. "XXX" means the value of E1E0EN. So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7. Signed-off-by: Zhiyong Tao --- drivers/pinctrl/mediatek/pinctrl-mt8183.c | 50 ++++++++++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 49 +++++++++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 11 ++++++ drivers/pinctrl/mediatek/pinctrl-paris.c | 21 ++++++++++ 4 files changed, 131 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c index 6262fd3678ea..2c7409ed16fa 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c @@ -472,6 +472,51 @@ static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = { PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1), }; +static const struct mtk_pin_field_calc mt8183_pin_e1e0en_range[] = { + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 20, 1), + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 15, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 7, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 12, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 9, 1), + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 19, 1), + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 22, 1), + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 24, 1), + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 14, 1), + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 27, 1), + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 17, 1), +}; + +static const struct mtk_pin_field_calc mt8183_pin_e0_range[] = { + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 21, 1), + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 16, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 13, 1), + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 8, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 13, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 10, 1), + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 20, 1), + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 23, 1), + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 25, 1), + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 15, 1), + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 28, 1), + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt8183_pin_e1_range[] = { + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 22, 1), + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 14, 1), + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 14, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 21, 1), + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 24, 1), + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 26, 1), + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 16, 1), + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 29, 1), + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 19, 1), +}; + static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range), @@ -485,6 +530,9 @@ static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range), [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range), [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range), + [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8183_pin_e1e0en_range), + [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8183_pin_e0_range), + [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8183_pin_e1_range), }; static const char * const mt8183_pinctrl_register_base_names[] = { @@ -517,6 +565,8 @@ static const struct mtk_pin_soc mt8183_data = { .drive_get = mtk_pinconf_drive_get_rev1, .adv_pull_get = mtk_pinconf_adv_pull_get, .adv_pull_set = mtk_pinconf_adv_pull_set, + .adv_drive_get = mtk_pinconf_adv_drive_get, + .adv_drive_set = mtk_pinconf_adv_drive_set, }; static const struct of_device_id mt8183_pinctrl_of_match[] = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index b1c368455d30..20e1c890e73b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -674,3 +674,52 @@ int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, return 0; } + +int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 arg) +{ + int err; + int en = arg & 1; + int e0 = !!(arg & 2); + int e1 = !!(arg & 4); + + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en); + if (err) + return err; + + if (!en) + return err; + + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0); + if (err) + return err; + + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); + if (err) + return err; + + return err; +} + +int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 *val) +{ + u32 en, e0, e1; + int err; + + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en); + if (err) + return err; + + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0); + if (err) + return err; + + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1); + if (err) + return err; + + *val = (en | e0 << 1 | e1 << 2) & 0x7; + + return 0; +} diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index 6d24522739d9..1b7da42aa1d5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -63,6 +63,9 @@ enum { PINCTRL_PIN_REG_IES, PINCTRL_PIN_REG_PULLEN, PINCTRL_PIN_REG_PULLSEL, + PINCTRL_PIN_REG_DRV_EN, + PINCTRL_PIN_REG_DRV_E0, + PINCTRL_PIN_REG_DRV_E1, PINCTRL_PIN_REG_MAX, }; @@ -224,6 +227,10 @@ struct mtk_pin_soc { int (*adv_pull_get)(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, u32 *val); + int (*adv_drive_set)(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 arg); + int (*adv_drive_get)(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 *val); /* Specific driver data */ void *driver_data; @@ -287,5 +294,9 @@ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, u32 *val); +int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 arg); +int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 *val); #endif /* __PINCTRL_MTK_COMMON_V2_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index b59e10852bfb..d3b34e9a7507 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -20,12 +20,14 @@ #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3) #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4) +#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5) static const struct pinconf_generic_params mtk_custom_bindings[] = { {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1}, {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1}, + {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2}, }; #ifdef CONFIG_DEBUG_FS @@ -34,6 +36,7 @@ static const struct pin_config_item mtk_conf_items[] = { PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true), PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true), + PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true), }; #endif @@ -176,6 +179,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, return -ENOTSUPP; } break; + case MTK_PIN_CONFIG_DRV_ADV: + if (hw->soc->adv_drive_get) { + err = hw->soc->adv_drive_get(hw, desc, &ret); + if (err) + return err; + } else { + return -ENOTSUPP; + } + break; default: return -ENOTSUPP; } @@ -311,6 +323,15 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return -ENOTSUPP; } break; + case MTK_PIN_CONFIG_DRV_ADV: + if (hw->soc->adv_drive_set) { + err = hw->soc->adv_drive_set(hw, desc, arg); + if (err) + return err; + } else { + return -ENOTSUPP; + } + break; default: err = -ENOTSUPP; }