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[3/3] ARM: dts: sunxi: Improve sun8i NAND transfers by using DMA

Message ID 20190404162111.22618-4-miquel.raynal@bootlin.com
State New, archived
Headers show
Series Sun8i NAND DMA support | expand

Commit Message

Miquel Raynal April 4, 2019, 4:21 p.m. UTC
In the current state, sun8i NAND controllers use PIO during
transfers. Throughput can be increased thanks to the use of DMA
(mostly during reads, because of the ECC pipelining feature).

Besides the usual addition of DMA DT properties, because the sun8i
NAND DMA handling is different than for older SoCs, we must also
update the compatible which has recently been introduced for this
purpose.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Maxime Ripard April 5, 2019, 9:18 a.m. UTC | #1
On Thu, Apr 04, 2019 at 06:21:11PM +0200, Miquel Raynal wrote:
> In the current state, sun8i NAND controllers use PIO during
> transfers. Throughput can be increased thanks to the use of DMA
> (mostly during reads, because of the ECC pipelining feature).
>
> Besides the usual addition of DMA DT properties, because the sun8i

The only thing that "sun8i" means for Allwinner is that the SoC has
Cortex-A7 CPUs. You need to be more precise than that, why not just
use A33?

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Miquel Raynal April 5, 2019, 9:38 a.m. UTC | #2
Hi Maxime,

Maxime Ripard <maxime.ripard@bootlin.com> wrote on Fri, 5 Apr 2019
11:18:07 +0200:

> On Thu, Apr 04, 2019 at 06:21:11PM +0200, Miquel Raynal wrote:
> > In the current state, sun8i NAND controllers use PIO during
> > transfers. Throughput can be increased thanks to the use of DMA
> > (mostly during reads, because of the ECC pipelining feature).
> >
> > Besides the usual addition of DMA DT properties, because the sun8i  
> 
> The only thing that "sun8i" means for Allwinner is that the SoC has
> Cortex-A7 CPUs. You need to be more precise than that, why not just
> use A33?

I am always confused. I'll stick to A33 then.


Thanks,
Miquèl
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 14a7d0288b45..f928b4bceb22 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -162,11 +162,13 @@ 
 		};
 
 		nfc: nand@1c03000 {
-			compatible = "allwinner,sun4i-a10-nand";
+			compatible = "allwinner,sun8i-a33-nand-controller";
 			reg = <0x01c03000 0x1000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
 			clock-names = "ahb", "mod";
+			dmas = <&dma 5>;
+			dma-names = "rxtx";
 			resets = <&ccu RST_BUS_NAND>;
 			reset-names = "ahb";
 			pinctrl-names = "default";