From patchwork Mon Apr 8 07:41:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10888923 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEEDB1708 for ; Mon, 8 Apr 2019 07:43:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92FA326E7B for ; Mon, 8 Apr 2019 07:43:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8747827C2D; Mon, 8 Apr 2019 07:43:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 20CE426E7B for ; Mon, 8 Apr 2019 07:43:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pvbUg7p1Dfk9a4zZaJMrrp7dG1gsJkkyrNMued3v1Rg=; b=PbeIeUeDN8wQIb SSVVQVgIJfOne5wcm7zuOjcUwX6qaBO+pm5AfzDfbM6DL+9sq5JFLhI/Sv4KxuBDf9gA5lsHj761m vUTqGQ078Mo4+EO6UdicZOsLZ+/I7b7C60TAG2Bqt90gT4uiboU3an+C2Mmljxl+DkBqtutE4TzKp UYVZlDNGrzkxyhJ9XwX59N2ZKNR6SNm7GNjvY7O9Zfv9lWsJG9hYA/1JQKpQPH8gfMgBMIcP7DvDP 9UNVCbCM3HOrg45RD+aOmhOlnLQrWytytx0tt/oA6CMz1FSzNqlpCMwY06auWDVSJWxUTZRBIxH94 urHdAaJgKQWee7ag37dA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hDOwE-0003KO-DX; Mon, 08 Apr 2019 07:43:30 +0000 Received: from relay5-d.mail.gandi.net ([217.70.183.197]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hDOul-0001PP-Hd; Mon, 08 Apr 2019 07:42:28 +0000 X-Originating-IP: 90.88.30.125 Received: from localhost.localdomain (aaubervilliers-681-1-89-125.w90-88.abo.wanadoo.fr [90.88.30.125]) (Authenticated sender: miquel.raynal@bootlin.com) by relay5-d.mail.gandi.net (Postfix) with ESMTPSA id AC4C31C0008; Mon, 8 Apr 2019 07:41:55 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , David Woodhouse , Brian Norris , Marek Vasut , Tudor Ambarus , Vignesh Raghavendra , , Rob Herring , Mark Rutland , Subject: [PATCH v2 3/4] mtd: rawnand: sunxi: Add A33 DMA support Date: Mon, 8 Apr 2019 09:41:46 +0200 Message-Id: <20190408074147.26797-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190408074147.26797-1-miquel.raynal@bootlin.com> References: <20190408074147.26797-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190408_004200_763639_160DF4ED X-CRM114-Status: GOOD ( 19.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxime Ripard , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, Miquel Raynal Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Allwinner NAND controllers can make use of DMA to enhance the I/O throughput thanks to ECC pipelining. DMA handling with A33 NAND IP is a bit different than with the older SoCs, hence the introduction of a new compatible to handle: * the differences between register offsets, * the burst length change from 4 to minimum 8, * drive SRAM accesses through the AHB bus instead of the MBUS. Signed-off-by: Miquel Raynal --- Changes in v2: * Enumerate the SoCs already supported (A10, A10s, A13 and A20) instead of using the inaccurate acronym 'A10+'. * s/p.12 of the user manual/p.12 of the *NFC* user manual/ * s/sun8i/A33/ drivers/mtd/nand/raw/sunxi_nand.c | 38 +++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 7b824c245083..18fa30175d67 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -43,6 +43,7 @@ #define NFC_REG_RCMD_SET 0x0028 #define NFC_REG_WCMD_SET 0x002C #define NFC_REG_A10_IO_DATA 0x0030 +#define NFC_REG_A33_IO_DATA 0x0300 #define NFC_REG_ECC_CTL 0x0034 #define NFC_REG_ECC_ST 0x0038 #define NFC_REG_DEBUG 0x003C @@ -204,10 +205,14 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand) * NAND Controller capabilities structure: stores NAND controller capabilities * for distinction between compatible strings. * + * @sram_through_ahb: On A33, we choose to access the internal RAM through AHB + * instead of MBUS (less configuration). A10, A10s, A13 and + * A20 use the MBUS but no extra configuration is needed. * @reg_io_data: I/O data register * @dma_maxburst: DMA maxburst */ struct sunxi_nfc_caps { + bool sram_through_ahb; unsigned int reg_io_data; unsigned int dma_maxburst; }; @@ -363,10 +368,29 @@ static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf, goto err_unmap_buf; } - writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD, - nfc->regs + NFC_REG_CTL); + /* + * On A33, we suppose the "internal RAM" (p.12 of the NFC user manual) + * refers to the NAND controller's internal SRAM. This memory is mapped + * and so is accessible from the AHB. It seems that it can also be + * accessed by the MBUS. MBUS accesses are mandatory when using the + * internal DMA instead of the external DMA engine. + * + * During DMA I/O operation, either we access this memory from the AHB + * by clearing the NFC_RAM_METHOD bit, or we set the bit and use the + * MBUS. In this case, we should also configure the MBUS DMA length + * NFC_REG_MDMA_CNT(0xC4) to be chunksize * nchunks. NAND I/O over MBUS + * are also limited to 32kiB pages. + */ + if (nfc->caps->sram_through_ahb) + writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD, + nfc->regs + NFC_REG_CTL); + else + writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD, + nfc->regs + NFC_REG_CTL); + writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM); writel(chunksize, nfc->regs + NFC_REG_CNT); + dmat = dmaengine_submit(dmad); ret = dma_submit_error(dmat); @@ -2176,11 +2200,21 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = { .dma_maxburst = 4, }; +static const struct sunxi_nfc_caps sunxi_nfc_a33_caps = { + .sram_through_ahb = true, + .reg_io_data = NFC_REG_A33_IO_DATA, + .dma_maxburst = 8, +}; + static const struct of_device_id sunxi_nfc_ids[] = { { .compatible = "allwinner,sun4i-a10-nand", .data = &sunxi_nfc_a10_caps, }, + { + .compatible = "allwinner,sun8i-a33-nand-controller", + .data = &sunxi_nfc_a33_caps, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);