From patchwork Thu Apr 11 10:19:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 10895571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0AA89186D for ; Thu, 11 Apr 2019 10:20:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E426128891 for ; Thu, 11 Apr 2019 10:20:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D78C528CC3; Thu, 11 Apr 2019 10:20:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.4 required=2.0 tests=BAYES_00,DKIM_ADSP_DISCARD, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4E4B628C69 for ; Thu, 11 Apr 2019 10:20:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kEmNUYGKzJdbYR49UeppbFbBOW4/j3HEMd2uxBB+3dA=; b=gpmiAjEF6P7BA7 HckskaHMVHgqekSXXnNzRAN7XEknCH20osEodwA6fZ2+4MtiUGjI+BIOvTQhz3C4sJERrlQSmvQOw U71h1dIDYUY6Us6blsSUAsQrmb9TU67GCS+6EG0EJhDEBggGnKLRPWo/ZoO0rBKAIBzmVD21mOtvj Dwm0CI3FasuMv55XYHN8XUoupjA61WdCIAWCMFY/DZVxrVDYVCjQ8bMRvnex7aWgPxKQEp/VQ8C1F /LjnGrE+pPtd6k+miQ/zMyOBkny2UFjRl/h15S1tVhUSHSRfzCKrvS6vqHU/iwV0vao8klHL0xkRX 2Dbrr3O5S1JnVlxN/iLA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEWoR-0006S6-W1; Thu, 11 Apr 2019 10:20:08 +0000 Received: from vps.xff.cz ([195.181.215.36]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEWoK-0006NL-DL for linux-arm-kernel@lists.infradead.org; Thu, 11 Apr 2019 10:20:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554977996; bh=//Y9g6FyC9JeT0oJjFckG39umOxcy3nQRVaTbv9yQdc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UZ/3N3NXudgSWaEaZ1WVknpjen7QYUsm4mZNrs58RmLQ18Ej7tvtbPgC6oq7sKny9 2XVrvVT34Wjo64BNOwZHuiV6o+DGFfcFQ7O1PdrXXffByd+rm0l/veBWY4GstRbEYN c9wniYueWtPlirCLW3VcFr3X1C3sR8EDNRzkeANc= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Subject: [PATCH v3 04/11] pinctrl: sunxi: Support I/O bias voltage setting on H6 Date: Thu, 11 Apr 2019 12:19:44 +0200 Message-Id: <20190411101951.30223-5-megous@megous.com> In-Reply-To: <20190411101951.30223-1-megous@megous.com> References: <20190411101951.30223-1-megous@megous.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190411_032001_677588_51CDD6C2 X-CRM114-Status: GOOD ( 12.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , Mark Rutland , David Airlie , Chi-Hsien Lin , dri-devel@lists.freedesktop.org, linux-stm32@st-md-mailman.stormreply.com, brcm80211-dev-list@cypress.com, Jose Abreu , Naveen Gupta , devicetree@vger.kernel.org, Arend van Spriel , Alexandre Torgue , Hante Meuleman , linux-gpio@vger.kernel.org, Wright Feng , Giuseppe Cavallaro , linux-arm-kernel@lists.infradead.org, Franky Lin , Maxime Coquelin , brcm80211-dev-list.pdl@broadcom.com, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org, Kalle Valo , Daniel Vetter , "David S. Miller" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ondrej Jirman H6 SoC has a "pio group withstand voltage mode" register (datasheet description), that needs to be used to select either 1.8V or 3.3V I/O mode, based on what voltage is powering the respective pin banks and is thus used for I/O signals. Add support for configuring this register according to the voltage of the pin bank regulator (if enabled). This is similar to the support for I/O bias voltage setting patch for A80 and the same concerns apply. See: commit 402bfb3c1352 ("Support I/O bias voltage setting on A80") Signed-off-by: Ondrej Jirman Acked-by: Maxime Ripard --- drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 11 +++++++++++ drivers/pinctrl/sunxi/pinctrl-sunxi.h | 5 +++++ 3 files changed, 17 insertions(+) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c index ef4268cc6227..3cc1121589c9 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = { .irq_banks = 4, .irq_bank_map = h6_irq_bank_map, .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; static int h6_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 98c4de5f4019..0cbca30b75dc 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -614,6 +614,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, unsigned pin, struct regulator *supply) { + unsigned short bank = pin / PINS_PER_BANK; + unsigned long flags; u32 val, reg; int uV; @@ -651,6 +653,15 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, reg &= ~IO_BIAS_MASK; writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); return 0; + case BIAS_VOLTAGE_PIO_POW_MODE_SEL: + val = uV <= 1800000 ? 1 : 0; + + raw_spin_lock_irqsave(&pctl->lock, flags); + reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); + reg &= ~(1 << bank); + writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); + raw_spin_unlock_irqrestore(&pctl->lock, flags); + return 0; default: return -EINVAL; } diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 4bfc8a6d9dce..36186906f0a7 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -95,11 +95,16 @@ #define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN8I_R40 BIT(8) +#define PIO_POW_MOD_SEL_REG 0x340 + enum sunxi_desc_bias_voltage { BIAS_VOLTAGE_NONE, /* Bias voltage configuration is done through * Pn_GRP_CONFIG registers, as seen on A80 SoC. */ BIAS_VOLTAGE_GRP_CONFIG, + /* Bias voltage is set through PIO_POW_MOD_SEL_REG + * register, as seen on H6 SoC, for example. */ + BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; struct sunxi_desc_function {