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bh=cSD6PBow7v0W8TwFUmI5O2Pxk6CBw7ocNAAJAAXdWg8=; b=s6BKTPrGZ74GuBWlNDzm2z5ZwD56LDAX1Pvb0N6CgNBIDT+Cfda6XmlvSp44zCbNj4 7PvAE/OuDT7OP9S+IpbL2TjW/ez+JXKJ4QpI0G428wolTpzGOTEBXhZMloZT16JEMkGj aPC3Kjii8nSP7c2mPTkG3I6yCKZttaUF7g7DvLPBINxcd8khpVli0MnejnLDTLClz7pN Iw5DTna/RIy8ZeJoO5+ceRVDB2TTJUMWNBahLHyiRTzN+n3qbHvSwgSueirGex7Eqbin /vybO6Gas13wLvBhANiFdez1NKEA7EeAIlrNGPZ3MyhzQ00fkY72n8sZoNtuxheqaGjq qDkQ== X-Gm-Message-State: APjAAAVleYeJXYYSDP7XROcP8SGOiY6QbplJtjUIZcUWOuSj58roDm2z luwIH5y5xhwTVEDYiHo+T+M= X-Google-Smtp-Source: APXvYqzNxdl1PhIO1oOobESMBfrW0DrNzXt6hIBogeVrQpk/WjkC/3DOHfN+kDsMgbMux6PsbVAqxA== X-Received: by 2002:a7b:cd95:: with SMTP id y21mr21860173wmj.29.1555323052152; Mon, 15 Apr 2019 03:10:52 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.10.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:10:51 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Subject: [PATCH RFT V2 1/8] clk: divider: add explicit big endian support Date: Mon, 15 Apr 2019 12:10:39 +0200 Message-Id: <20190415101046.5872-2-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_031053_767686_88298398 X-CRM114-Status: GOOD ( 15.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter De Schrijver , Fabio Estevam , Heiko Stuebner , Stephen Boyd , Benjamin Herrenschmidt , Michael Turquette , Michal Simek , Jonathan Hunter , Prashant Gaikwad , Paul Mackerras , NXP Linux Team , Pengutronix Kernel Team , Michael Ellerman , Thierry Reding , Anatolij Gustschin , Shawn Guo , Sascha Hauer MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian divider clocks. Signed-off-by: Jonas Gorski --- V1 -> V2: * switch from global to local flag drivers/clk/clk-divider.c | 26 ++++++++++++++++++++++---- include/linux/clk-provider.h | 4 ++++ 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index e5a17265cfaf..ff791a7a5e9e 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -25,6 +25,24 @@ * parent - fixed parent. No clk_set_parent support */ +static inline u32 clk_div_readl(struct clk_divider *divider) +{ + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + return ioread32be(divider->reg); + else + return clk_readl(divider->reg); +} + +static inline void clk_div_writel(struct clk_divider *divider, u32 val) +{ + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + iowrite32be(val, divider->reg); + else + clk_writel(val, divider->reg); +} + +#define div_mask(width) ((1 << (width)) - 1) + static unsigned int _get_table_maxdiv(const struct clk_div_table *table, u8 width) { @@ -135,7 +153,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); unsigned int val; - val = clk_readl(divider->reg) >> divider->shift; + val = clk_div_readl(divider) >> divider->shift; val &= clk_div_mask(divider->width); return divider_recalc_rate(hw, parent_rate, val, divider->table, @@ -370,7 +388,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_READ_ONLY) { u32 val; - val = clk_readl(divider->reg) >> divider->shift; + val = clk_div_readl(divider->reg) >> divider->shift; val &= clk_div_mask(divider->width); return divider_ro_round_rate(hw, rate, prate, divider->table, @@ -420,11 +438,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { val = clk_div_mask(divider->width) << (divider->shift + 16); } else { - val = clk_readl(divider->reg); + val = clk_div_readl(divider->reg); val &= ~(clk_div_mask(divider->width) << divider->shift); } val |= (u32)value << divider->shift; - clk_writel(val, divider->reg); + clk_div_writel(divider, val); if (divider->lock) spin_unlock_irqrestore(divider->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index db21437c77e2..7117b8cc0c0c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -416,6 +416,9 @@ struct clk_div_table { * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. + * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used + * for the divider register. Setting this flag makes the register accesses + * big endian. */ struct clk_divider { struct clk_hw hw; @@ -437,6 +440,7 @@ struct clk_divider { #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_DIVIDER_BIG_ENDIAN BIT(7) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops;