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bh=0DzTJysZxO15MPQ7kqYMW+n479fJgtxXcOuK6TSaMOY=; b=dC90SmfHypluS5vJm7R/8z963VsCXWtQq7yKXGwIaPTeWL9G4ukD/+VucN1xXUPGhw RLwHcbgiWb2iPRCIwpNQVJBdp7rvihq2laUWOoBcyoTnymlY96MeIZ5eNFvKJgjitPB3 tp7FtqSqhLt77jWccl24vsUFDgOVifWitxQZB31d38JqmkQgngcanu7bbLYPCTVg8YAF bHAvJ+1dpBvyfWrzR4mCGkLtzjaPyV5w7Y/E4p/fmA3Fb56hv7PNFc4pdrh00lbyxiJq fWpCUF4pAYyjWnPNkhx/nPCgQORxcSbFHZrjqD+BA5ayb9ncZSEpCKZ8sjH587EvIbEF Xyig== X-Gm-Message-State: APjAAAW3Kk4NADwwTdRUG422PbAXTWBbMKYpnxNfLFoHJRQlo/b8/Aas uDgRdYssGbFlKdI7PH3P4q0= X-Google-Smtp-Source: APXvYqxsvH0Rc7MHGSQ5oXiwFD2EUfMonfSwzm6bqTZnIhCPTVMeStUOT1R7Tz14Ms6g+WEJB2kWAw== X-Received: by 2002:a05:600c:24f:: with SMTP id 15mr22249991wmj.48.1555323056233; Mon, 15 Apr 2019 03:10:56 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.10.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:10:55 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Subject: [PATCH RFT V2 3/8] clk: gate: add explicit big endian support Date: Mon, 15 Apr 2019 12:10:41 +0200 Message-Id: <20190415101046.5872-4-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_031057_934764_63198021 X-CRM114-Status: GOOD ( 15.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter De Schrijver , Fabio Estevam , Heiko Stuebner , Stephen Boyd , Benjamin Herrenschmidt , Michael Turquette , Michal Simek , Jonathan Hunter , Prashant Gaikwad , Paul Mackerras , NXP Linux Team , Pengutronix Kernel Team , Michael Ellerman , Thierry Reding , Anatolij Gustschin , Shawn Guo , Sascha Hauer MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian gated clocks. Signed-off-by: Jonas Gorski --- V1 -> V2: * switch from global to local flag drivers/clk/clk-gate.c | 22 +++++++++++++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index f05823cd9b21..521e112ef5b5 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -23,6 +23,22 @@ * parent - fixed parent. No clk_set_parent support */ +static inline u32 clk_gate_readl(struct clk_gate *gate) +{ + if (gate->flags & CLK_GATE_BIG_ENDIAN) + return ioread32be(gate->reg); + else + return clk_readl(gate->reg); +} + +static inline void clk_gate_writel(struct clk_gate *gate, u32 val) +{ + if (gate->flags & CLK_GATE_BIG_ENDIAN) + iowrite32be(val, gate->reg); + else + clk_writel(val, gate->reg); +} + /* * It works on following logic: * @@ -55,7 +71,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) if (set) reg |= BIT(gate->bit_idx); } else { - reg = clk_readl(gate->reg); + reg = clk_gate_readl(gate); if (set) reg |= BIT(gate->bit_idx); @@ -63,7 +79,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) reg &= ~BIT(gate->bit_idx); } - clk_writel(reg, gate->reg); + clk_gate_writel(gate, reg); if (gate->lock) spin_unlock_irqrestore(gate->lock, flags); @@ -88,7 +104,7 @@ int clk_gate_is_enabled(struct clk_hw *hw) u32 reg; struct clk_gate *gate = to_clk_gate(hw); - reg = clk_readl(gate->reg); + reg = clk_gate_readl(gate); /* if a set bit disables this clk, flip it before masking */ if (gate->flags & CLK_GATE_SET_TO_DISABLE) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 8c07d810acf5..8576c2dbc639 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -348,6 +348,9 @@ void of_fixed_clk_setup(struct device_node *np); * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. + * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for + * the gate register. Setting this flag makes the register accesses big + * endian. */ struct clk_gate { struct clk_hw hw; @@ -361,6 +364,7 @@ struct clk_gate { #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) +#define CLK_GATE_BIG_ENDIAN BIT(2) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name,