| Message ID | 20190415165030.15270-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mq: fixes for Zii Ultra board | expand |
On Mon, Apr 15, 2019 at 06:50:30PM +0200, Lucas Stach wrote: > - fix eMMC signaling issues > - fix touchscreen node name > - fix PCIe clock description > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > Shawn, if possible just squash this into the commit adding the Zii > Ultra boards. Those are fixes for some issues I discovered when > re-testing the board support with some more recent bits of the > i.MX8M upstream driver support. Done, with a small change below. > --- > .../dts/freescale/imx8mq-zii-ultra-rmb3.dts | 2 +- > .../boot/dts/freescale/imx8mq-zii-ultra.dtsi | 66 ++++++++++++------- > 2 files changed, 45 insertions(+), 23 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts > index 7442f7f7fcba..d2a6da479980 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts > @@ -66,7 +66,7 @@ > }; > }; > > - eeti_touch: eeti_i2c@2a { > + touchscreen@2a { > compatible = "eeti,exc3000"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_ts>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > index f34c9d1f635f..b577c5e7f808 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > @@ -93,6 +93,18 @@ > 900000 0x1>; > regulator-always-on; > }; > + > + pcie0_refclk: pcie0-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; > + > + pcie1_refclk: pcie1-refclk { I renamed the nodes as clock-pcie0-refclk and clock-pcie0-refclk, moved them above regulator nodes (for sake of alphabetic order). Shawn > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; > }; > > &A53_0 { > @@ -439,6 +451,11 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_pcie0>; > reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; > + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, > + <&clk IMX8MQ_CLK_PCIE1_AUX>, > + <&clk IMX8MQ_CLK_PCIE1_PHY>, > + <&pcie0_refclk>; > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; > status = "okay"; > }; > > @@ -446,6 +463,11 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_pcie1>; > reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; > + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, > + <&clk IMX8MQ_CLK_PCIE2_AUX>, > + <&clk IMX8MQ_CLK_PCIE2_PHY>, > + <&pcie1_refclk>; > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; > status = "okay"; > }; > > @@ -633,34 +655,34 @@ > > pinctrl_usdhc1_100mhz: usdhc1-100grp { > fsl,pins = < > - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 > - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 > - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 > - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 > - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 > - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 > - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 > - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 > - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 > - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 > - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 > + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d > + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd > + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd > + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd > + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd > + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd > + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd > + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd > + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd > + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd > + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d > MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 > >; > }; > > pinctrl_usdhc1_200mhz: usdhc1-200grp { > fsl,pins = < > - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 > - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 > - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 > - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 > - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 > - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 > - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 > - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 > - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 > - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 > - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 > + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f > + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf > + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf > + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf > + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf > + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf > + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf > + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf > + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf > + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf > + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f > MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 > >; > }; > -- > 2.20.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts index 7442f7f7fcba..d2a6da479980 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts @@ -66,7 +66,7 @@ }; }; - eeti_touch: eeti_i2c@2a { + touchscreen@2a { compatible = "eeti,exc3000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ts>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index f34c9d1f635f..b577c5e7f808 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -93,6 +93,18 @@ 900000 0x1>; regulator-always-on; }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; }; &A53_0 { @@ -439,6 +451,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; status = "okay"; }; @@ -446,6 +463,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; status = "okay"; }; @@ -633,34 +655,34 @@ pinctrl_usdhc1_100mhz: usdhc1-100grp { fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 >; }; pinctrl_usdhc1_200mhz: usdhc1-200grp { fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 >; };
- fix eMMC signaling issues - fix touchscreen node name - fix PCIe clock description Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- Shawn, if possible just squash this into the commit adding the Zii Ultra boards. Those are fixes for some issues I discovered when re-testing the board support with some more recent bits of the i.MX8M upstream driver support. --- .../dts/freescale/imx8mq-zii-ultra-rmb3.dts | 2 +- .../boot/dts/freescale/imx8mq-zii-ultra.dtsi | 66 ++++++++++++------- 2 files changed, 45 insertions(+), 23 deletions(-)