From patchwork Mon Apr 15 18:05:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 10901329 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC1BF1515 for ; Mon, 15 Apr 2019 18:05:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F79228553 for ; Mon, 15 Apr 2019 18:05:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8317328591; Mon, 15 Apr 2019 18:05:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 192AF28553 for ; Mon, 15 Apr 2019 18:05:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:To: From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=lrIGhYO35Z5gEQG6IEKvUF6TvYtn0Uh3O6JLkwHagSg=; b=hKLJdvCuBbYx2c HhxWm2dN4qniVXWjGJeLDn25MTtx9icx9MOBoTISwX+4Um5aQqH7Zp2dVuSi0TEaCH0kdKK4qDz4s n0Me8n6OjHDHK9b+IoutQpHs+dKEf8cWBocLZdyzFJbZTQQfHA3P5OS9fxSIwN6ciaLjXyJxIvMUb KhGIoM8zUU7q4Qn+mVl9EbabGNkmS3vt1O4pzZ6qVYP9iI1BsKu9jGHPcxbLTXkMfkIL/cod/Gt84 brBsncA+UihjzJaWqn3SXMZzflMVJMDYLTcFPYNxHHbbvpS3H6bEnvVEcDnwsiKAiT9rotZdJRsYJ qCQsTbXhHcXBs02QeFdw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hG5yv-0006qT-MX; Mon, 15 Apr 2019 18:05:25 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hG5ys-0006pv-9E for linux-arm-kernel@lists.infradead.org; Mon, 15 Apr 2019 18:05:23 +0000 Received: from localhost.localdomain (unknown [194.230.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 78738218A1; Mon, 15 Apr 2019 18:05:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1555351521; bh=2WzjGWG/IuZjdiWRfgwSv89YnhMwA3Iqa1iAqPLab9U=; h=From:To:Subject:Date:From; b=WamA2y8M+9vMWU+NYKA10XH0qATIybeOBg5fRfB+HNxnxBqkN5EhefZshV8eNBp6g 8THiKkO0cNp62Yi+5nUXE+Y4OA9ld+XencN4PmNAtcE2PwW8tD1aChpPAYpo4pcfGO JcNxZvaNaFj0yeofyC2N2ltp+1seBYT1MLJb4KLY= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Sylwester Nawrocki , Chanwoo Choi , Andrzej Hajda , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] ARM: dts: exynos: Move pmu and timer nodes out of soc Date: Mon, 15 Apr 2019 20:05:07 +0200 Message-Id: <20190415180510.6044-1-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_110522_362385_1AFEE39C X-CRM114-Status: GOOD ( 16.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The ARM PMU and ARM architected timer nodes are part of ARM CPU design therefore they should not be inside the soc node. This also fixes DTC W=1 warnings like: arch/arm/boot/dts/exynos3250.dtsi:106.21-135.5: Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property arch/arm/boot/dts/exynos3250.dtsi:676.7-680.5: Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski --- arch/arm/boot/dts/exynos3250.dtsi | 12 +++++----- arch/arm/boot/dts/exynos4.dtsi | 12 +++++----- arch/arm/boot/dts/exynos5250.dtsi | 40 +++++++++++++++---------------- arch/arm/boot/dts/exynos54xx.dtsi | 38 ++++++++++++++--------------- 4 files changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 5892a9f7622f..af54b306204b 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -97,6 +97,12 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -673,12 +679,6 @@ status = "disabled"; }; - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - }; - ppmu_dmc0: ppmu_dmc0@106a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106a0000 0x2000>; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 6085e92ac2d7..1c21627e3c3c 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -51,6 +51,12 @@ serial3 = &serial_3; }; + pmu: pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&combiner>; + interrupts = <2 2>, <3 2>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -169,12 +175,6 @@ reg = <0x10440000 0x1000>; }; - pmu: pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&combiner>; - interrupts = <2 2>, <3 2>; - }; - sys_reg: syscon@10010000 { compatible = "samsung,exynos4-sysreg", "syscon"; reg = <0x10010000 0x400>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 80986b97dfe5..96ace6a5e2f9 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -157,6 +157,26 @@ }; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, <22 4>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + /* + * Unfortunately we need this since some versions + * of U-Boot on Exynos don't set the CNTFRQ register, + * so we need the value from DT. + */ + clock-frequency = <24000000>; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram"; @@ -227,20 +247,6 @@ power-domains = <&pd_mau>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - /* - * Unfortunately we need this since some versions - * of U-Boot on Exynos don't set the CNTFRQ register, - * so we need the value from DT. - */ - clock-frequency = <24000000>; - }; - mct@101c0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; @@ -265,12 +271,6 @@ }; }; - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, <22 4>; - }; - pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos5250-pinctrl"; reg = <0x11400000 0x1000>; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index de26e5ee0d2d..ae866bcc30c4 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -25,27 +25,27 @@ usbdrdphy1 = &usbdrd_phy1; }; - soc: soc { - arm_a7_pmu: arm-a7-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - status = "disabled"; - }; + arm_a7_pmu: arm-a7-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + status = "disabled"; + }; - arm_a15_pmu: arm-a15-pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, - <7 0>, - <16 6>, - <19 2>; - status = "disabled"; - }; + arm_a15_pmu: arm-a15-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, + <7 0>, + <16 6>, + <19 2>; + status = "disabled"; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x54000>;