| Message ID | 20190416060501.76276-4-jitao.shi@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support dsi for mt8183 | expand |
Hi, Jitao: On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote: > New DSI IP has shadow register and working reg. The register > values are writen to shadow register. And then trigger with > commit reg, the register values will be moved working register. This patch looks good, but the message is not complete. The message make us believe you use shadow register to work, but actually, shadow register is default turn on in new DSI IP and you want to turn off it. Regards, CK > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index 573e6bec6d36..be42405a0a78 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -131,6 +131,10 @@ > #define VM_CMD_EN BIT(0) > #define TS_VFP_EN BIT(5) > > +#define DSI_SHADOW_DEBUG 0x190U > +#define FORCE_COMMIT BIT(0) > +#define BYPASS_SHADOW BIT(1) > + > #define CONFIG (0xff << 0) > #define SHORT_PACKET 0 > #define LONG_PACKET 2 > @@ -157,6 +161,7 @@ struct phy; > > struct mtk_dsi_driver_data { > const u32 reg_cmdq_off; > + bool has_shadow_ctl; > }; > > struct mtk_dsi { > @@ -594,6 +599,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > } > > mtk_dsi_enable(dsi); > + > + if (dsi->driver_data->has_shadow_ctl) > + writel(FORCE_COMMIT | BYPASS_SHADOW, > + dsi->regs + DSI_SHADOW_DEBUG); > + > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); >
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 573e6bec6d36..be42405a0a78 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -131,6 +131,10 @@ #define VM_CMD_EN BIT(0) #define TS_VFP_EN BIT(5) +#define DSI_SHADOW_DEBUG 0x190U +#define FORCE_COMMIT BIT(0) +#define BYPASS_SHADOW BIT(1) + #define CONFIG (0xff << 0) #define SHORT_PACKET 0 #define LONG_PACKET 2 @@ -157,6 +161,7 @@ struct phy; struct mtk_dsi_driver_data { const u32 reg_cmdq_off; + bool has_shadow_ctl; }; struct mtk_dsi { @@ -594,6 +599,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) } mtk_dsi_enable(dsi); + + if (dsi->driver_data->has_shadow_ctl) + writel(FORCE_COMMIT | BYPASS_SHADOW, + dsi->regs + DSI_SHADOW_DEBUG); + mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi);
New DSI IP has shadow register and working reg. The register values are writen to shadow register. And then trigger with commit reg, the register values will be moved working register. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ 1 file changed, 10 insertions(+)