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Wed, 17 Apr 2019 05:27:40 +0000 From: Jacky Bai To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "l.stach@pengutronix.de" , Aisheng Dong Subject: [PATCH 3/3] arm64: dts: freescale: Add power domain nodes for i.mx8mm Thread-Topic: [PATCH 3/3] arm64: dts: freescale: Add power domain nodes for i.mx8mm Thread-Index: AQHU9N5GBOJqX2r8sUmx0rA3TW1YDQ== Date: Wed, 17 Apr 2019 05:27:40 +0000 Message-ID: <20190417053211.2195-4-ping.bai@nxp.com> References: <20190417053211.2195-1-ping.bai@nxp.com> In-Reply-To: <20190417053211.2195-1-ping.bai@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.21.0 x-clientproxiedby: HK0PR01CA0031.apcprd01.prod.exchangelabs.com (2603:1096:203:3e::19) To VI1PR0402MB3519.eurprd04.prod.outlook.com (2603:10a6:803:8::24) authentication-results: spf=none (sender IP is ) smtp.mailfrom=ping.bai@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.71] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 48bcff6e-5045-4737-0d94-08d6c2f568f7 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Signed-off-by: Jacky Bai --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 103 ++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index de3498c2dd44..49af5181e17f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -149,6 +149,109 @@ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; + power-domains { + compatible = "simple-bus"; + /* HSIO SS */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <0>; + domain-name = "hsiomix"; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + }; + + pcie_pd: pcie-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <1>; + domain-name = "pcie"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg1_pd: usbotg1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg2_pd: usbotg2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <3>; + domain-name = "usb_otg2"; + parent-domains = <&hsiomix_pd>; + }; + + /* GPU SS */ + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <4>; + domain-name = "gpumix"; + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + }; + + /* VPU SS */ + vpumix_pd: vpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "vpumix"; + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + }; + + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: vpug2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <7>; + domain-name = "vpu_g2"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: vpuh1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <8>; + domain-name = "vpu_h1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; + }; + + /* DISP SS */ + dispmix_pd: dispmix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <9>; + domain-name = "dispmix"; + clocks = <&clk IMX8MM_CLK_DISP_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: mipi-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <10>; + domain-name = "mipi"; + parent-domains = <&dispmix_pd>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , /* Physical Secure */