| Message ID | 20190513035909.30460-2-andrew.smirnov@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] ARM: dts: vf610-zii-dev: Fix incorrect UART2 pin assignment | expand |
Hi Andrey, On Mon, May 13, 2019 at 12:59 AM Andrey Smirnov <andrew.smirnov@gmail.com> wrote: > +&qspi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_qspi0>; > + status = "okay"; > + > + /* > + * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in SDR > + * modes, so we limit spi-max-frequency to 90Mhz Nit: It is MHz, not Mhz. MT25QL02 datasheet refers to DTR and STR (not SDR). Also, the public datasheet I can see online lists these limits differently: "• Clock frequency – 133 MHz (MAX) for all protocols in STR – 66 MHz (MAX) for all protocols in DTR"
On Mon, May 13, 2019 at 5:15 AM Fabio Estevam <festevam@gmail.com> wrote: > > Hi Andrey, > > On Mon, May 13, 2019 at 12:59 AM Andrey Smirnov > <andrew.smirnov@gmail.com> wrote: > > > +&qspi0 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_qspi0>; > > + status = "okay"; > > + > > + /* > > + * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in SDR > > + * modes, so we limit spi-max-frequency to 90Mhz > > Nit: It is MHz, not Mhz. > > MT25QL02 datasheet refers to DTR and STR (not SDR). > Sure, will fix. > Also, the public datasheet I can see online lists these limits differently: > > "• Clock frequency – 133 MHz (MAX) for all protocols in STR – 66 MHz > (MAX) for all protocols in DTR" Here's the datasheet I got those numbers from: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf Thanks, Andrey Smirnov
diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 5246c75e848c..f63a470f78ce 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -177,6 +177,36 @@ status = "okay"; }; +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + status = "okay"; + + /* + * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in SDR + * modes, so we limit spi-max-frequency to 90Mhz + */ + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <90000000>; + spi-rx-bus-width = <4>; + reg = <0>; + m25p,fast-read; + }; + + flash@2 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <90000000>; + spi-rx-bus-width = <4>; + reg = <2>; + m25p,fast-read; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -360,12 +390,18 @@ pinctrl_qspi0: qspi0grp { fsl,pins = < - VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 - VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff - VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 - VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 - VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 - VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 + VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2 + VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2 + VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3 + VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3 + VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3 + VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3 + VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2 + VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2 + VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3 >; };
Both rev C and rev B of the board come with two QSPI-NOR chips attached to the SoC. Add DT code describing all of this. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm/boot/dts/vf610-zii-dev.dtsi | 48 ++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 6 deletions(-)