| Message ID | 20190529211340.17087-6-atish.patra@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Unify CPU topology across ARM & RISC-V | expand |
On Wed, 29 May 2019, Atish Patra wrote: > Currently, there are no topology defined for RISC-V. > Parse the cpu-map node from device tree and setup the > cpu topology. > > CPU topology after applying the patch. > $cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list > 0-3 > $cat /sys/devices/system/cpu/cpu3/topology/core_siblings_list > 0-3 > $cat /sys/devices/system/cpu/cpu3/topology/physical_package_id > 0 > $cat /sys/devices/system/cpu/cpu3/topology/core_id > 3 > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > Acked-by: Sudeep Holla <sudeep.holla@arm.com> Looks reasonable to me. Acked-by: Paul Walmsley <paul.walmsley@sifive.com> We're assuming, on the RISC-V side, that these patches will go in via another tree. - Paul
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0c4b12205632..2d8a16299a85 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -47,6 +47,7 @@ config RISCV select PCI_MSI if PCI select RISCV_TIMER select GENERIC_IRQ_MULTI_HANDLER + select GENERIC_ARCH_TOPOLOGY if SMP select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_MMIOWB select HAVE_EBPF_JIT if 64BIT diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 7a0b62252524..54f89d5b19ba 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <linux/arch_topology.h> #include <linux/module.h> #include <linux/init.h> #include <linux/kernel.h> @@ -43,6 +44,7 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { + init_cpu_topology(); } void __init smp_prepare_cpus(unsigned int max_cpus) @@ -146,6 +148,7 @@ asmlinkage void __init smp_callin(void) trap_init(); notify_cpu_starting(smp_processor_id()); + update_siblings_masks(smp_processor_id()); set_cpu_online(smp_processor_id(), 1); /* * Remote TLB flushes are ignored while the CPU is offline, so emit