From patchwork Tue Jun 4 02:35:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10974141 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 203D314E5 for ; Tue, 4 Jun 2019 02:35:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0CBCA286B9 for ; Tue, 4 Jun 2019 02:35:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F41BD28764; Tue, 4 Jun 2019 02:35:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 18223286B9 for ; Tue, 4 Jun 2019 02:35:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=wxzreoHV1LO+CpNMkFvihkNVS9ebFn3p/PdiuQC2Gtc=; b=eJMpUbw4+/U+d0 7uNNtBqt4hCzuiVSFybopSOFx4zup8VvNhNxi00XNwr9CH3FVI9mLx/tpns5MyAebSwx/SU9h30Tf IuE2RG5fbVrPS1+UfazNgcmxquodoJoRbchzKgRk4Gol4ztt2z0ZgFChZBuwXczd1qLEyhWvPilm/ nIXNZhBZb2YSiOia9AbCtdCK1LSX8+n2uDOSZtzY1cTsxdfA5iz+lsSzj21ilbxrp5b8VVyU/+R1C el95fRzo6yuOQKr0FIdTupGfyZKE5DHRuuTUNjR9JJtKJQw3F+02cLcfiY2aeM8xALym6Rp/nBEX+ ZZu8KBC8gKq1WkIS1JgA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hXzIf-00041B-9K; Tue, 04 Jun 2019 02:35:45 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hXzIc-00040f-Ca for linux-arm-kernel@lists.infradead.org; Tue, 04 Jun 2019 02:35:43 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 03 Jun 2019 19:35:38 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 03 Jun 2019 19:35:39 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 03 Jun 2019 19:35:39 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 4 Jun 2019 02:35:39 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 4 Jun 2019 02:35:38 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 4 Jun 2019 02:35:38 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 03 Jun 2019 19:35:38 -0700 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH] arm64: tegra: add CPU cache topology for Tegra186 Date: Tue, 4 Jun 2019 10:35:35 +0800 Message-ID: <20190604023535.7115-1-josephl@nvidia.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1559615738; bh=AmoNdluQeX3k2IWG+5yEa3tuSV9eSMqeTaMre8hA2sc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=PfvFfsYvBjBPMBICFj850oIPuFNbI+4lWuy3JTXDpYALRFPTyW/PZ/WDU963aAheJ u2iCEl8UH+19bNRUw0MAtChrQxGT05vSGpCEu3ZgrrpcnUL8qhmQi0ULJwyfYaDG67 IQiHUSkkiTdsras+StyU/9LCszNZDqYfrYBmBvYp3ejS9I9fihALc+lVOFq7k9eNxi rMIpAZcnX75/LpfmobhOoQzjJQhn/+oYzocXBuk3WEItxQvyDQUAVLLA3piwJ4ayIv Oniz63K1DF+i4p80F7ljwuOWa2wZQFF9121SrWOANPQEHcj3GrezYPmVaC+7hKGMPW CelZgORJksfWw== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190603_193542_437850_0B96FD8F X-CRM114-Status: UNSURE ( 6.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra186 has two CPU clusters with its own cache hierarchy. This patch adds them with the cache information of each of the CPUs. Signed-off-by: Joseph Lo --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 426ac0bdf6a6..26055c7f26e7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1128,38 +1128,52 @@ cpu@0 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; + next-level-cache = <&L2_DENVER>; reg = <0x000>; }; cpu@1 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; + next-level-cache = <&L2_DENVER>; reg = <0x001>; }; cpu@2 { compatible = "arm,cortex-a57"; device_type = "cpu"; + next-level-cache = <&L2_A57>; reg = <0x100>; }; cpu@3 { compatible = "arm,cortex-a57"; device_type = "cpu"; + next-level-cache = <&L2_A57>; reg = <0x101>; }; cpu@4 { compatible = "arm,cortex-a57"; device_type = "cpu"; + next-level-cache = <&L2_A57>; reg = <0x102>; }; cpu@5 { compatible = "arm,cortex-a57"; device_type = "cpu"; + next-level-cache = <&L2_A57>; reg = <0x103>; }; + + L2_DENVER: l2-cache0 { + compatible = "cache"; + }; + + L2_A57: l2-cache1 { + compatible = "cache"; + }; }; bpmp: bpmp {