| Message ID | 20190611140940.14357-12-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support for Allwinner V3/S3L and Sochip S3 | expand |
Hi, On Tue, Jun 11, 2019 at 10:09:40PM +0800, Icenowy Zheng wrote: > Lichee zero plus is a core board made by Sipeed, which includes on-board > TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug > header, a microUSB slot and a gold finger connector for expansion. It > can use either Sochip S3 or Allwinner S3L SoC. > > Add the basic device tree for the core board, w/o optional onboard > storage, and with S3 SoC. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > New patch in v2. > > arch/arm/boot/dts/Makefile | 1 + > .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ > .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 39 +++++++++++++++++++ > 3 files changed, 48 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 5559028b770e..2b5e6a1d20ff 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1110,6 +1110,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > sun8i-r16-nintendo-super-nes-classic.dtb \ > sun8i-r16-parrot.dtb \ > sun8i-r40-bananapi-m2-ultra.dtb \ > + sun8i-s3-lichee-zero-plus.dtb \ > sun8i-t3-cqa3t-bv3.dtb \ > sun8i-v3s-licheepi-zero.dtb \ > sun8i-v3s-licheepi-zero-dock.dtb \ > diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > new file mode 100644 > index 000000000000..7d2f6b145190 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +/dts-v1/; > +#include "sun8i-s3.dtsi" > +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > new file mode 100644 > index 000000000000..bb148e796df7 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > @@ -0,0 +1,39 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sunxi-common-regulators.dtsi" If possible, you should get rid of that include. What are you using it for? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5559028b770e..2b5e6a1d20ff 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1110,6 +1110,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts new file mode 100644 index 000000000000..7d2f6b145190 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +/dts-v1/; +#include "sun8i-s3.dtsi" +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi new file mode 100644 index 000000000000..bb148e796df7 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +#include "sunxi-common-regulators.dtsi" + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +};
Lichee zero plus is a core board made by Sipeed, which includes on-board TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug header, a microUSB slot and a gold finger connector for expansion. It can use either Sochip S3 or Allwinner S3L SoC. Add the basic device tree for the core board, w/o optional onboard storage, and with S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- New patch in v2. arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 39 +++++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi