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[66.187.233.206]) by smtp.gmail.com with ESMTPSA id z57sm6538533qta.62.2019.06.11.08.19.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 08:19:38 -0700 (PDT) From: Masayoshi Mizuma To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] arm64/mm: check cpu cache line size with non-coherent device Date: Tue, 11 Jun 2019 11:17:30 -0400 Message-Id: <20190611151731.6135-2-msys.mizuma@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190611151731.6135-1-msys.mizuma@gmail.com> References: <20190611151731.6135-1-msys.mizuma@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190611_081940_694233_54FA52A5 X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Masayoshi Mizuma , Hidetoshi Seto , Masayoshi Mizuma , linux-kernel@vger.kernel.org, Zhang Lei MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Masayoshi Mizuma As discussed in the thread [1], the cpu cache line size will be problem only on non-coherent devices. And, the coherent flag is already introduced to struct device. Show the warning only if the device is non-coherent device and ARCH_DMA_MINALIGN is smaller than the cpu cache size. [1] https://lore.kernel.org/linux-arm-kernel/20180514145703.celnlobzn3uh5tc2@localhost/ Signed-off-by: Masayoshi Mizuma Reviewed-by: Hidetoshi Seto Tested-by: Zhang Lei --- arch/arm64/mm/dma-mapping.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 674860e3e478..c0c09890c845 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -91,10 +91,6 @@ static int __swiotlb_mmap_pfn(struct vm_area_struct *vma, static int __init arm64_dma_init(void) { - WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(), - TAINT_CPU_OUT_OF_SPEC, - "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", - ARCH_DMA_MINALIGN, cache_line_size()); return dma_atomic_pool_init(GFP_DMA32, __pgprot(PROT_NORMAL_NC)); } arch_initcall(arm64_dma_init); @@ -473,6 +469,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, const struct iommu_ops *iommu, bool coherent) { dev->dma_coherent = coherent; + + if (!coherent && (cache_line_size() > ARCH_DMA_MINALIGN)) + dev_WARN(dev, "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", + ARCH_DMA_MINALIGN, cache_line_size()); + __iommu_setup_dma_ops(dev, dma_base, size, iommu); #ifdef CONFIG_XEN