From patchwork Tue Jun 18 07:02:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 11001003 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B934014B6 for ; Tue, 18 Jun 2019 07:03:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A50DD288D3 for ; Tue, 18 Jun 2019 07:03:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 96CAC28A14; Tue, 18 Jun 2019 07:03:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0CC0A288D3 for ; Tue, 18 Jun 2019 07:03:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jfca+FTdd7Ki0HOcnQlC4TroCp+jMQ1v2P4kYWR0w7E=; b=YppRaBy/jVnwJZ +LPNdt39q/Pj7GwsUkI1jIDQ06tfushkhGSHdlZ4tgXTc3ciWO0930gBjycbXfLviZJSc95ZsxcVY BvpPuhUMSKBl9fneSx7uvE0ZaI92W7IjspflYoUtXe3DM4BgTlYxe1dopYo5lWzixf6oQWeOboZ73 5pd+5pC/wuHMQvAlvss5JKGvREaSUDGUBLqHOOA/1osupzz9bDA34nhFFqe2G9yp4CxpY+B6FHMrB AmTCfqOsYxU6sMTK2jg/KpTQQwkfrtFqsMjPZ212Q2zfc4GfCMmmD6CBt3jsUu1kVEOcR0srvME5V UUcwU9BtjZYlpxsRHUYw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hd89B-0007IJ-RX; Tue, 18 Jun 2019 07:03:13 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hd898-0007HO-Kw; Tue, 18 Jun 2019 07:03:12 +0000 X-UUID: 1c83e47165c4405d982482d081f5e20f-20190617 X-UUID: 1c83e47165c4405d982482d081f5e20f-20190617 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1809378283; Mon, 17 Jun 2019 23:03:06 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 18 Jun 2019 00:03:04 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 18 Jun 2019 15:03:02 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 18 Jun 2019 15:03:02 +0800 From: Roger Lu To: Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd Subject: [PATCH v2 1/2] dt-bindings: soc: add mtk svs dt-bindings Date: Tue, 18 Jun 2019 15:02:57 +0800 Message-ID: <20190618070258.11520-2-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190618070258.11520-1-roger.lu@mediatek.com> References: <20190618070258.11520-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 35EA4D0BD3B99E1485275D69B076854751F01C2EB3410F62FB3B4FA4EBFF0B412000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190618_000310_689636_7067008D X-CRM114-Status: GOOD ( 10.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Nishanth Menon , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Roger Lu , linux-kernel@vger.kernel.org, HenryC Chen , Fan Chen , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Document the binding for enabling mtk svs on MediaTek SoC. Signed-off-by: Roger Lu --- .../devicetree/bindings/power/mtk-svs.txt | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/mtk-svs.txt diff --git a/Documentation/devicetree/bindings/power/mtk-svs.txt b/Documentation/devicetree/bindings/power/mtk-svs.txt new file mode 100644 index 000000000000..6a71992ef162 --- /dev/null +++ b/Documentation/devicetree/bindings/power/mtk-svs.txt @@ -0,0 +1,88 @@ +* Mediatek Smart Voltage Scaling (MTK SVS) + +This describes the device tree binding for the MTK SVS controller (bank) +which helps provide the optimized CPU/GPU/CCI voltages. This device also +needs thermal data to calculate thermal slope for accurately compensate +the voltages when temperature change. + +Required properties: +- compatible: + - "mediatek,mt8183-svs" : For MT8183 family of SoCs +- reg: Address range of the MTK SVS controller. +- interrupts: IRQ for the MTK SVS controller. +- clocks, clock-names: Clocks needed for the svs controller. required + clocks are: + "main_clk": Main clock needed for register access +- nvmem-cells: Phandle to the calibration data provided by a nvmem device. +- nvmem-cell-names: Should be "svs-calibration-data" and "calibration-data" + +Subnodes: +- svs_cpu_little: SVS bank device node of little CPU + compatible: "mediatek,mt8183-svs-cpu-little" + operating-points-v2: OPP table hooked by SVS little CPU bank. + SVS will optimze this OPP table voltage part. + vcpu-little-supply: PMIC buck of little CPU +- svs_cpu_big: SVS bank device node of big CPU + compatible: "mediatek,mt8183-svs-cpu-big" + operating-points-v2: OPP table hooked by SVS big CPU bank. + SVS will optimze this OPP table voltage part. + vcpu-big-supply: PMIC buck of big CPU +- svs_cci: SVS bank device node of CCI + compatible: "mediatek,mt8183-svs-cci" + operating-points-v2: OPP table hooked by SVS CCI bank. + SVS will optimze this OPP table voltage part. + vcci-supply: PMIC buck of CCI +- svs_gpu: SVS bank device node of GPU + compatible: "mediatek,mt8183-svs-gpu" + operating-points-v2: OPP table hooked by SVS GPU bank. + SVS will optimze this OPP table voltage part. + vgpu-spply: PMIC buck of GPU + +Example: + + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main_clk"; + nvmem-cells = <&svs_calibration>, <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", "calibration-data"; + + svs_cpu_little: svs_cpu_little { + compatible = "mediatek,mt8183-svs-cpu-little"; + operating-points-v2 = <&cluster0_opp>; + }; + + svs_cpu_big: svs_cpu_big { + compatible = "mediatek,mt8183-svs-cpu-big"; + operating-points-v2 = <&cluster1_opp>; + }; + + svs_cci: svs_cci { + compatible = "mediatek,mt8183-svs-cci"; + operating-points-v2 = <&cci_opp>; + }; + + svs_gpu: svs_gpu { + compatible = "mediatek,mt8183-svs-gpu"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>; + operating-points-v2 = <&gpu_opp_table>; + }; + }; + + &svs_cpu_little { + vcpu-little-supply = <&mt6358_vproc12_reg>; + }; + + &svs_cpu_big { + vcpu-big-supply = <&mt6358_vproc11_reg>; + }; + + &svs_cci { + vcci-supply = <&mt6358_vproc12_reg>; + }; + + &svs_gpu { + vgpu-spply = <&mt6358_vgpu_reg>; + };