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Wed, 26 Jun 2019 03:15:58 -0400 (EDT) From: Andrew Jeffery To: linux-gpio@vger.kernel.org Subject: [PATCH 5/8] pinctrl: aspeed: Correct comment that is no longer true Date: Wed, 26 Jun 2019 16:44:27 +0930 Message-Id: <20190626071430.28556-6-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190626071430.28556-1-andrew@aj.id.au> References: <20190626071430.28556-1-andrew@aj.id.au> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190626_001604_141763_9B147AA1 X-CRM114-Status: UNSURE ( 8.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, ryan_chen@aspeedtech.com, linux-aspeed@lists.ozlabs.org, Andrew Jeffery , linus.walleij@linaro.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, joel@jms.id.au, openbmc@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We have handled the GFX register case for quite some time now. Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley --- drivers/pinctrl/aspeed/pinctrl-aspeed.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 4b06ddbc6aec..c5918c4a087c 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -240,8 +240,7 @@ * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions * reference registers beyond those dedicated to pinmux, such as the system * reset control and MAC clock configuration registers. The AST2500 goes a step - * further and references registers in the graphics IP block, but that isn't - * handled yet. + * further and references registers in the graphics IP block. */ #define SCU2C 0x2C /* Misc. Control Register */ #define SCU3C 0x3C /* System Reset Control/Status Register */