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Received: from mailgw02.mediatek.com ([216.200.240.185]) by casper.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hgKdC-0005hx-O9; Thu, 27 Jun 2019 02:59:29 +0000 X-UUID: a5ad35c79c7948f5bde3797443b8d27a-20190626 X-UUID: a5ad35c79c7948f5bde3797443b8d27a-20190626 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1479419976; Wed, 26 Jun 2019 18:59:10 -0800 Received: from MTKMBS33N1.mediatek.inc (172.27.4.75) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Jun 2019 19:59:08 -0700 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 27 Jun 2019 10:59:06 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 27 Jun 2019 10:59:04 +0800 From: Jitao Shi To: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , , David Airlie , "Matthias Brugger" Subject: [v5 1/3] dt-bindings: display: mediatek: update dsi supported chips Date: Thu, 27 Jun 2019 10:58:59 +0800 Message-ID: <20190627025901.28418-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190627025901.28418-1-jitao.shi@mediatek.com> References: <20190627025901.28418-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190627_035927_092380_1B823176 X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stonea168@163.com, dri-devel@lists.freedesktop.org, Andy Yan , Ajay Kumar , Rob Herring , Vincent Palatin , cawa.cheng@mediatek.com, bibby.hsieh@mediatek.com, ck.hu@mediatek.com, Russell King , Thierry Reding , devicetree@vger.kernel.org, Jitao Shi , Philipp Zabel , Inki Dae , linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org, Rahul Sharma , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Sascha Hauer , Sean Paul Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Update device tree binding documentation for the dsi for Mediatek MT8183 SoCs. Signed-off-by: Jitao Shi Acked-by: Rob Herring --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index fadf327c7cdf..a19a6cc375ed 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. Required properties: - compatible: "mediatek,-dsi" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder