| Message ID | 20190627122505.25774-2-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enhance CP110 COMPHY support | expand |
On Thu, Jun 27, 2019 at 02:25:00PM +0200, Miquel Raynal wrote: > Armada CP110 PCIe controller can have a PHY (for configuring SERDES > lanes). Describe these two properties in the bindings. > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > --- > Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > index 9e3fc15e1af8..a373a80524db 100644 > --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt > +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > @@ -17,6 +17,10 @@ Required properties: > name must be "core" for the first clock and "reg" for the second > one > > +Optional properties: > +- phys: phandle to the PHY node (generic PHY bindings). > +- phy-names: names of the PHYs. How many? If only 1, you don't really need phy-names. > + > Example: > > pcie@f2600000 { > -- > 2.19.1 >
Hi Rob, Rob Herring <robh@kernel.org> wrote on Mon, 22 Jul 2019 11:52:25 -0600: > On Thu, Jun 27, 2019 at 02:25:00PM +0200, Miquel Raynal wrote: > > Armada CP110 PCIe controller can have a PHY (for configuring SERDES > > lanes). Describe these two properties in the bindings. > > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > > --- > > Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > index 9e3fc15e1af8..a373a80524db 100644 > > --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > @@ -17,6 +17,10 @@ Required properties: > > name must be "core" for the first clock and "reg" for the second > > one > > > > +Optional properties: > > +- phys: phandle to the PHY node (generic PHY bindings). > > +- phy-names: names of the PHYs. > > How many? If only 1, you don't really need phy-names. I thought it was preferred to always add phy-names, but ok, I'll drop the property. Thanks, Miquèl
Hi Rob, Rob Herring <robh@kernel.org> wrote on Mon, 22 Jul 2019 11:52:25 -0600: > On Thu, Jun 27, 2019 at 02:25:00PM +0200, Miquel Raynal wrote: > > Armada CP110 PCIe controller can have a PHY (for configuring SERDES > > lanes). Describe these two properties in the bindings. > > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > > --- > > Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > index 9e3fc15e1af8..a373a80524db 100644 > > --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > @@ -17,6 +17,10 @@ Required properties: > > name must be "core" for the first clock and "reg" for the second > > one > > > > +Optional properties: > > +- phys: phandle to the PHY node (generic PHY bindings). > > +- phy-names: names of the PHYs. > > How many? If only 1, you don't really need phy-names. Actually it depends on the board. For instance, the MacchiatoBin has four of them: --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -186,6 +186,10 @@ reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; + phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, + <&cp0_comphy2 0>, <&cp0_comphy3 0>; + phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", + "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy"; status = "okay"; }; Thanks, Miquèl
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 9e3fc15e1af8..a373a80524db 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -17,6 +17,10 @@ Required properties: name must be "core" for the first clock and "reg" for the second one +Optional properties: +- phys: phandle to the PHY node (generic PHY bindings). +- phy-names: names of the PHYs. + Example: pcie@f2600000 {
Armada CP110 PCIe controller can have a PHY (for configuring SERDES lanes). Describe these two properties in the bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++ 1 file changed, 4 insertions(+)