| Message ID | 20190701091258.3870-15-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | arm64: g12a: add support for DVFS | expand |
On Mon, Jul 1, 2019 at 11:13 AM Neil Armstrong <narmstrong@baylibre.com> wrote: > > Enable DVFS for the Odroid-N2 by setting the clock, OPP and supply > for each cores of each CPU clusters. > > The first cluster uses the "VDDCPU_B" power supply, and the second > cluster uses the "VDDCPU_A" power supply. > > Each power supply can achieve 0.73V to 1.01V using 2 distinct PWM > outputs clocked at 800KHz with an inverse duty-cycle. > > DVFS has been tested by running the arm64 cpuburn at [1] and cycling > between all the possible cpufreq translations of each cluster and > checking the final frequency using the clock-measurer, script at [2]. > > [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S > [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [...] > + vddcpu_b: regulator-vddcpu-b { > + /* > + * Silergy SY8120B1ABC Regulator. > + */ interesting that they use different regulator ICs for CPU A and CPU B the public schematics confirm your comments
On 03/07/2019 01:45, Martin Blumenstingl wrote: > On Mon, Jul 1, 2019 at 11:13 AM Neil Armstrong <narmstrong@baylibre.com> wrote: >> >> Enable DVFS for the Odroid-N2 by setting the clock, OPP and supply >> for each cores of each CPU clusters. >> >> The first cluster uses the "VDDCPU_B" power supply, and the second >> cluster uses the "VDDCPU_A" power supply. >> >> Each power supply can achieve 0.73V to 1.01V using 2 distinct PWM >> outputs clocked at 800KHz with an inverse duty-cycle. >> >> DVFS has been tested by running the arm64 cpuburn at [1] and cycling >> between all the possible cpufreq translations of each cluster and >> checking the final frequency using the clock-measurer, script at [2]. >> >> [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S >> [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f >> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > > [...] >> + vddcpu_b: regulator-vddcpu-b { >> + /* >> + * Silergy SY8120B1ABC Regulator. >> + */ > interesting that they use different regulator ICs for CPU A and CPU B > the public schematics confirm your comments > Yep they use a Silergy one for VDDCPU_B on every schematics I have. The A311D VIM3 have a slightly different one, but still Silergy for VDDCPU_B. https://dl.khadas.com/Hardware/VIM3/Schematic/VIM3_V11_Sch.pdf Neil
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts index 81780ffcc7f0..75ff8a7e373d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts @@ -114,6 +114,44 @@ /* FIXME: actually controlled by VDDCPU_B_EN */ }; + vddcpu_a: regulator-vddcpu-a { + /* + * MP8756GD Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_A"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_ab 0 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddcpu_b: regulator-vddcpu-b { + /* + * Silergy SY8120B1ABC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_B"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + hub_5v: regulator-hub_5v { compatible = "regulator-fixed"; regulator-name = "HUB_5V"; @@ -245,6 +283,48 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu100 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu101 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu102 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu103 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + &ext_mdio { external_phy: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ @@ -316,6 +396,22 @@ pinctrl-names = "default"; }; +&pwm_ab { + pinctrl-0 = <&pwm_a_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; + status = "okay"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + /* SD card */ &sd_emmc_b { status = "okay";
Enable DVFS for the Odroid-N2 by setting the clock, OPP and supply for each cores of each CPU clusters. The first cluster uses the "VDDCPU_B" power supply, and the second cluster uses the "VDDCPU_A" power supply. Each power supply can achieve 0.73V to 1.01V using 2 distinct PWM outputs clocked at 800KHz with an inverse duty-cycle. DVFS has been tested by running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of each cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+)