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Mon, 15 Jul 2019 12:44:45 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 16/50] clk: samsung: add SPLL rate table in Exynos5420 Date: Mon, 15 Jul 2019 14:43:43 +0200 Message-Id: <20190715124417.4787-17-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHKsWRmVeSWpSXmKPExsWy7djP87r2pTqxBtNvylrcWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KC6blNSczLLUIn27BK6M5o0vWAve81ecvLCAsYFxL28XIyeH hICJRNvrz6xdjFwcQgIrGCUWb33CBuF8YZS4t2s5lPOZUeLqn0mMMC2bJv6GSixnlDi4/DYj XMucD2uBMhwcbAJ6EjtWFYI0iAgsYZQ48jMJpIZZ4CaTxJ4nO1lBEsICnhI9i3qYQWwWAVWJ RT9us4PYvAL2Eq8W72KH2CYvsXrDAbAaTqD4z2kXwDZLCJxjl5jR38cKUeQisfT0YyYIW1ji 1fEtUM0yEqcn97BA2MUSDb0LoV6okXjcPxeqxlri8PGLrCBHMwtoSqzfpQ8RdpT41TidGSQs IcAnceOtIEiYGcictA0mzCvR0SYEUa0hsaXnAtQBYhLL10yDGu4hsWbRaRZI8ExilHjfMYdt AqP8LIRlCxgZVzGKp5YW56anFhvlpZbrFSfmFpfmpesl5+duYgSmqtP/jn/ZwbjrT9IhRgEO RiUeXocU7Vgh1sSy4srcQ4wSHMxKIry2X4FCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeasZHkQL CaQnlqRmp6YWpBbBZJk4OKUaGOUFVpRF5h8V3XP6bZNu9tPDlv2KPI5BNseO3ui0E1ZsmOhl l32XbdVsk3nq1odq30TVKvftUFarM9nktkz0yLaaB59dMz6bPmkx2Vcu+Z89Y8KSb8UOn9aH BJzgLWePmtXCO7/3euCPny0CAq4P4lbmPN7sU9ky6fTM1wtW6ivGmO2+s/OblhJLcUaioRZz UXEiAPtb1JxRAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPIsWRmVeSWpSXmKPExsVy+t/xe7p2pTqxBmt3qlvcWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1Ml fTublNSczLLUIn27BL2M5o0vWAve81ecvLCAsYFxL28XIyeHhICJxKaJv9lAbCGBpYwSj68Z Q8TFJCbt284OYQtL/LnWBVTDBVTziVHiz/vdrF2MHBxsAnoSO1YVgtSICKxglJh8whukhlng NZPEkaPvWEESwgKeEj2LephBbBYBVYlFP26DDeUVsJd4tXgX1AJ5idUbDoDVcALFf067AHWQ ncTioz+ZJjDyLWBkWMUoklpanJueW2ykV5yYW1yal66XnJ+7iREYOduO/dyyg7HrXfAhRgEO RiUeXocU7Vgh1sSy4srcQ4wSHMxKIry2X4FCvCmJlVWpRfnxRaU5qcWHGE2BjprILCWanA+M 6rySeENTQ3MLS0NzY3NjMwslcd4OgYMxQgLpiSWp2ampBalFMH1MHJxSDYwTznxzdFyx6O/p CavOO3pWa2cq2R+4dE5Ep1Z576JuqfuXdgovUirR2HSQeemMqVnp/hn+IWtORZhu2jpTbY7i 3Wdl21kPZStsPTNhhspOV98lR1vFlD1Kyg2kY1Nz9966fnufbfiiuwpXbVbuWxHYuD+hNueN 7HmbK1EXY+yztuXkzzq6+GuLEktxRqKhFnNRcSIAqCYO3rICAAA= X-CMS-MailID: 20190715124446eucas1p1b9b7ec3235fdd887bf5a253a4e223df0 X-Msg-Generator: CA X-RootMTR: 20190715124446eucas1p1b9b7ec3235fdd887bf5a253a4e223df0 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190715124446eucas1p1b9b7ec3235fdd887bf5a253a4e223df0 References: <20190715124417.4787-1-l.luba@partner.samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190715_054450_187095_1D8D96CF X-CRM114-Status: GOOD ( 13.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, cw00.choi@samsung.com, b.zolnierkie@samsung.com, sboyd@kernel.org, mturquette@baylibre.com, krzk@kernel.org, Lukasz Luba , a.hajda@samsung.com, robh+dt@kernel.org, kyungmin.park@samsung.com, kgene@kernel.org, myungjoo.ham@samsung.com, s.nawrocki@samsung.com, m.szyprowski@samsung.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The MPLL has fixed frequency left by the bootloader and it is not possible to change it. With this patch the SPLL gets rate table the same for the whole PLL family (similar as APLL, KPLL according to RM) so the frequency might be changed to one of the values defined there. It is needed for further patches which change the MPLL frequency to feed the clocks with proper base. It also sets CLK_IS_CRITICAL for SCLK_SPLL due to some drivers which could disable master clock, which is then populated higher and tries to disable PLL, which casues system crash. The flag is needed for this kind of use cases. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index cded46f360f1..ead569a164cf 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -690,7 +690,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX_F(CLK_MOUT_SCLK_MPLL, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1, CLK_IS_CRITICAL, 0), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), - MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), + MUX_F(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1, + CLK_IS_CRITICAL, 0), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, @@ -1520,6 +1521,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[mpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[spll].rate_table = exynos5420_pll2550x_24mhz_tbl; } if (soc == EXYNOS5420)