| Message ID | 20190731224149.11153-5-s-anna@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add TI PRUSS Local Interrupt Controller IRQChip driver | expand |
On 31/07/2019 23:41, Suman Anna wrote: > The PRUSS INTC receives a number of system input interrupt source events > and supports individual control configuration and hardware prioritization. > These input events can be mapped to some output interrupt lines through 2 > levels of many-to-one mapping i.e. events to channel mapping and channels > to output interrupts. > > This mapping information is provided through the PRU firmware that is > loaded onto a PRU core/s or through the device tree node of the PRU > application. The mapping is configured by the PRU remoteproc driver, and > is setup before the PRU core is started and cleaned up after the PRU core > is stopped. This event mapping configuration logic programs the Channel > Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a > new program is being loaded/started and the same events and interrupt > channels are reset to zero when stopping a PRU. > > Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure() > that the PRU remoteproc driver can use to configure the PRUSS INTC. So let me see if I correctly understand this: this adds yet another firmware description parser, with a private interface to another (undisclosed?) driver, bypassing the standard irqchip configuration mechanism. It sounds great, doesn't it? What I cannot really infer from this message (-ETOOMUCHJARGON) is what interrupts this affects: - Interrupts from random devices to the PRUSS? - Interrupts from the PRUSS to the host? - Something else? When does this happen? Under control of what? It isn't even clear why this is part of this irqchip driver. Depending what this does, there may be ways to fit it into the standard interrupt configuration framework. After all, we already have standard interfaces to route interrupts to virtual CPUs, effectively passing full control of an interrupt to another entity. If you squint hard enough, your PRUSS can fit that description. If that doesn't work, then we need to make the IRQ framework grok that kind of requirement (hence my request for clarification). But I'm strongly opposed to inventing a SoC-private way of configuring interrupts behind the kernel's back. Thanks, M.
Hi Marc, On 8/1/19 3:45 AM, Marc Zyngier wrote: > On 31/07/2019 23:41, Suman Anna wrote: >> The PRUSS INTC receives a number of system input interrupt source events >> and supports individual control configuration and hardware prioritization. >> These input events can be mapped to some output interrupt lines through 2 >> levels of many-to-one mapping i.e. events to channel mapping and channels >> to output interrupts. >> >> This mapping information is provided through the PRU firmware that is >> loaded onto a PRU core/s or through the device tree node of the PRU >> application. The mapping is configured by the PRU remoteproc driver, and >> is setup before the PRU core is started and cleaned up after the PRU core >> is stopped. This event mapping configuration logic programs the Channel >> Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a >> new program is being loaded/started and the same events and interrupt >> channels are reset to zero when stopping a PRU. >> >> Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure() >> that the PRU remoteproc driver can use to configure the PRUSS INTC. > > So let me see if I correctly understand this: this adds yet another > firmware description parser, with a private interface to another > (undisclosed?) driver, bypassing the standard irqchip configuration > mechanism. It sounds great, doesn't it? > > What I cannot really infer from this message (-ETOOMUCHJARGON) is what > interrupts this affects: > > - Interrupts from random devices to the PRUSS? > - Interrupts from the PRUSS to the host? > - Something else? The interrupt sources (called system events) can be from internal PRUSS peripherals, SoC-level peripherals or just software triggering (limited to some events). So, the PRUSS INTC behaves as a funnel and is both an interrupt router and multiplexer. The INTC itself is part of the PRUSS, and all PRU application related interrupts/events that need to trigger an interrupt to either the PRU cores or other host processors (like DSP, ARM) have to go through this INTC, and routed out to a limited number of output interrupts that are then connected to different processors. The split of interrupt handling between a PRU and its peer host processor will be a application design choice (We can implement soft IPs like UARTs, ADCs, I2Cs etc using PRUs). Some of the input events themselves are multiplexed and controlled by a single MMR (outside of INTC) that feeds different sets of events into the INTC. The MMR configuration is outside of scope of this driver and will depend on the application/client driver being run. > > When does this happen? Under control of what? It isn't even clear why > this is part of this irqchip driver. The mapping configuration is per PRU application and firmware, and is done in line with acquiring and release a PRU which is treated as an exclusive resource. We establish the mapping for all events through this driver including the events that are to be routed to PRUs. This is done to save the tiny/limited Instruction RAM space that PRUs have. We have designed this as an irqchip driver (instead of some custom SoC driver exporting custom functions) to use standard Linux semantics/irq API and better integrate with Linux DT, but we need some semantics for establishing the routing at runtime depending on the PRU client driver we are running. The exported functions will be called only by the PRU remoteproc driver during a pru_rproc_get()/pru_rproc_put(), and are transparent to PRU client drivers. Please also see the discussion from v1 [1] on why we can't use an extended number of interrupt-cells infrastructure for achieving this. [1] https://patchwork.kernel.org/patch/11034563/ > Depending what this does, there may be ways to fit it into the standard > interrupt configuration framework. After all, we already have standard > interfaces to route interrupts to virtual CPUs, effectively passing full > control of an interrupt to another entity. If you squint hard enough, > your PRUSS can fit that description. Yeah, I am open to suggestions if there is a better way of doing this. regards Suman > > If that doesn't work, then we need to make the IRQ framework grok that > kind of requirement (hence my request for clarification). But I'm > strongly opposed to inventing a SoC-private way of configuring > interrupts behind the kernel's back. > > Thanks, > > M. >
On 8/1/19 12:10 PM, Suman Anna wrote: > Hi Marc, > > On 8/1/19 3:45 AM, Marc Zyngier wrote: >> On 31/07/2019 23:41, Suman Anna wrote: >>> The PRUSS INTC receives a number of system input interrupt source events >>> and supports individual control configuration and hardware prioritization. >>> These input events can be mapped to some output interrupt lines through 2 >>> levels of many-to-one mapping i.e. events to channel mapping and channels >>> to output interrupts. >>> >>> This mapping information is provided through the PRU firmware that is >>> loaded onto a PRU core/s or through the device tree node of the PRU >>> application. The mapping is configured by the PRU remoteproc driver, and >>> is setup before the PRU core is started and cleaned up after the PRU core >>> is stopped. This event mapping configuration logic programs the Channel >>> Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a >>> new program is being loaded/started and the same events and interrupt >>> channels are reset to zero when stopping a PRU. >>> >>> Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure() >>> that the PRU remoteproc driver can use to configure the PRUSS INTC. >> >> So let me see if I correctly understand this: this adds yet another >> firmware description parser, with a private interface to another >> (undisclosed?) driver, bypassing the standard irqchip configuration >> mechanism. It sounds great, doesn't it? >> >> What I cannot really infer from this message (-ETOOMUCHJARGON) is what >> interrupts this affects: >> >> - Interrupts from random devices to the PRUSS? >> - Interrupts from the PRUSS to the host? >> - Something else? > > The interrupt sources (called system events) can be from internal PRUSS > peripherals, SoC-level peripherals or just software triggering (limited > to some events). > > So, the PRUSS INTC behaves as a funnel and is both an interrupt router > and multiplexer. The INTC itself is part of the PRUSS, and all PRU > application related interrupts/events that need to trigger an interrupt > to either the PRU cores or other host processors (like DSP, ARM) have to > go through this INTC, and routed out to a limited number of output > interrupts that are then connected to different processors. > > The split of interrupt handling between a PRU and its peer host > processor will be a application design choice (We can implement soft IPs > like UARTs, ADCs, I2Cs etc using PRUs). Some of the input events > themselves are multiplexed and controlled by a single MMR (outside of > INTC) that feeds different sets of events into the INTC. The MMR > configuration is outside of scope of this driver and will depend on the > application/client driver being run. > >> >> When does this happen? Under control of what? It isn't even clear why >> this is part of this irqchip driver. > > The mapping configuration is per PRU application and firmware, and is > done in line with acquiring and release a PRU which is treated as an > exclusive resource. We establish the mapping for all events through this > driver including the events that are to be routed to PRUs. This is done > to save the tiny/limited Instruction RAM space that PRUs have. > > We have designed this as an irqchip driver (instead of some custom SoC > driver exporting custom functions) to use standard Linux semantics/irq > API and better integrate with Linux DT, but we need some semantics for > establishing the routing at runtime depending on the PRU client driver > we are running. The exported functions will be called only by the PRU > remoteproc driver during a pru_rproc_get()/pru_rproc_put(), and are > transparent to PRU client drivers. > > Please also see the discussion from v1 [1] on why we can't use an > extended number of interrupt-cells infrastructure for achieving this. > > [1] https://patchwork.kernel.org/patch/11034563/ > > >> Depending what this does, there may be ways to fit it into the standard >> interrupt configuration framework. After all, we already have standard >> interfaces to route interrupts to virtual CPUs, effectively passing full >> control of an interrupt to another entity. If you squint hard enough, >> your PRUSS can fit that description. > > Yeah, I am open to suggestions if there is a better way of doing this. Hi Suman, Can you explain more about the use case where one PRU system event is mapped to multiple host events? I have an idea that we can use multiple struct irq_domains to make this work in the existing IRQ framework, but it would be helpful to know more about the bigger picture first. > > regards > Suman > >> >> If that doesn't work, then we need to make the IRQ framework grok that >> kind of requirement (hence my request for clarification). But I'm >> strongly opposed to inventing a SoC-private way of configuring >> interrupts behind the kernel's back. >> >> Thanks, >> >> M. >> >
Hi David, On 8/1/19 1:31 PM, David Lechner wrote: > On 8/1/19 12:10 PM, Suman Anna wrote: >> Hi Marc, >> >> On 8/1/19 3:45 AM, Marc Zyngier wrote: >>> On 31/07/2019 23:41, Suman Anna wrote: >>>> The PRUSS INTC receives a number of system input interrupt >>>> source events and supports individual control configuration and >>>> hardware prioritization. These input events can be mapped to >>>> some output interrupt lines through 2 levels of many-to-one >>>> mapping i.e. events to channel mapping and channels to output >>>> interrupts. >>>> >>>> This mapping information is provided through the PRU firmware >>>> that is loaded onto a PRU core/s or through the device tree >>>> node of the PRU application. The mapping is configured by the >>>> PRU remoteproc driver, and is setup before the PRU core is >>>> started and cleaned up after the PRU core is stopped. This >>>> event mapping configuration logic programs the Channel Map >>>> Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only >>>> when a new program is being loaded/started and the same events >>>> and interrupt channels are reset to zero when stopping a PRU. >>>> >>>> Add two helper functions: pruss_intc_configure() & >>>> pruss_intc_unconfigure() that the PRU remoteproc driver can use >>>> to configure the PRUSS INTC. >>> >>> So let me see if I correctly understand this: this adds yet >>> another firmware description parser, with a private interface to >>> another (undisclosed?) driver, bypassing the standard irqchip >>> configuration mechanism. It sounds great, doesn't it? >>> >>> What I cannot really infer from this message (-ETOOMUCHJARGON) is >>> what interrupts this affects: >>> >>> - Interrupts from random devices to the PRUSS? - Interrupts from >>> the PRUSS to the host? - Something else? >> >> The interrupt sources (called system events) can be from internal >> PRUSS peripherals, SoC-level peripherals or just software >> triggering (limited to some events). >> >> So, the PRUSS INTC behaves as a funnel and is both an interrupt >> router and multiplexer. The INTC itself is part of the PRUSS, and >> all PRU application related interrupts/events that need to trigger >> an interrupt to either the PRU cores or other host processors (like >> DSP, ARM) have to go through this INTC, and routed out to a limited >> number of output interrupts that are then connected to different >> processors. >> >> The split of interrupt handling between a PRU and its peer host >> processor will be a application design choice (We can implement >> soft IPs like UARTs, ADCs, I2Cs etc using PRUs). Some of the input >> events themselves are multiplexed and controlled by a single MMR >> (outside of INTC) that feeds different sets of events into the >> INTC. The MMR configuration is outside of scope of this driver and >> will depend on the application/client driver being run. >> >>> >>> When does this happen? Under control of what? It isn't even clear >>> why this is part of this irqchip driver. >> >> The mapping configuration is per PRU application and firmware, and >> is done in line with acquiring and release a PRU which is treated >> as an exclusive resource. We establish the mapping for all events >> through this driver including the events that are to be routed to >> PRUs. This is done to save the tiny/limited Instruction RAM space >> that PRUs have. >> >> We have designed this as an irqchip driver (instead of some custom >> SoC driver exporting custom functions) to use standard Linux >> semantics/irq API and better integrate with Linux DT, but we need >> some semantics for establishing the routing at runtime depending on >> the PRU client driver we are running. The exported functions will >> be called only by the PRU remoteproc driver during a >> pru_rproc_get()/pru_rproc_put(), and are transparent to PRU client >> drivers. >> >> Please also see the discussion from v1 [1] on why we can't use an >> extended number of interrupt-cells infrastructure for achieving >> this. >> >> [1] https://patchwork.kernel.org/patch/11034563/ >> >> >>> Depending what this does, there may be ways to fit it into the >>> standard interrupt configuration framework. After all, we already >>> have standard interfaces to route interrupts to virtual CPUs, >>> effectively passing full control of an interrupt to another >>> entity. If you squint hard enough, your PRUSS can fit that >>> description. >> >> Yeah, I am open to suggestions if there is a better way of doing >> this. > > Hi Suman, > > Can you explain more about the use case where one PRU system event > is mapped to multiple host events? On AM335x, for example, we have 64 events out of which events 16 to 31 are not sourced by any peripherals and are used for general purpose signaling between a PRU0/PRU1 core and any external host processor (like an ARM). So, different applications/drivers implementing a different soft IP like a Soft UART, Soft I2C, ADC etc will need to be using among these generic set to achieve their various interrupts / signaling logic between the corresponding ARM driver and the PRU firmware implementing the soft IP. Following are some existing usage examples on AM335x within TI SDKs (tuples of <system_event intr_channel output_interrupt> 1. A Soft UART implementing 3 ports per PRU: PRU0: <21, 2, 2>, <22, 3, 3>, <23, 4, 4> PRU1: <24, 5, 5>, <25, 6, 6>, <26, 7, 7>; 2. A Dual-EMAC PRU Ethernet usecase using one PRU per ethernet port utilizing the MDIO, MII_TI sub-modules within PRUSS: PRU0: {42, 0, 0}, {20, 2, 2}, {22, 4, 4}, {26, 6, 6}, {41, 7, 8}, PRU1: {54, 1, 1}, {21, 3, 3}, {23, 5, 5}, {53, 8, 9}, {27, 9, 7}, Some of the above PRU Ethernet ones are generic events while the others are tied to specific MII_RT interrupt events. A different mapping is used when both the ethernet ports and PRUs are being used to achieve a Switch functionality. Point is different applications might use mapping differently as per their firmware and driver/application design and their split across one or more PRUs (design by contract). And we need to set this up at runtime when the application driver is getting run. We will have either the Soft UART or the Ethernet running at a time depending on the end goal desired > I have an idea that we can use multiple struct irq_domains to make > this work in the existing IRQ framework, but it would be helpful to > know more about the bigger picture first. Yeah, would be great if there is a way this can be solved without having to introduce additional API. regards Suman > >> >> regards Suman >> >>> >>> If that doesn't work, then we need to make the IRQ framework grok >>> that kind of requirement (hence my request for clarification). >>> But I'm strongly opposed to inventing a SoC-private way of >>> configuring interrupts behind the kernel's back. >>> >>> Thanks, >>> >>> M. >>> >> >
On 8/2/19 4:26 PM, Suman Anna wrote: > Point is different applications might use mapping differently as per > their firmware and driver/application design and their split across one > or more PRUs (design by contract). And we need to set this up at runtime > when the application driver is getting run. We will have either the Soft > UART or the Ethernet running at a time depending on the end goal desired > >> I have an idea that we can use multiple struct irq_domains to make >> this work in the existing IRQ framework, but it would be helpful to >> know more about the bigger picture first. > > Yeah, would be great if there is a way this can be solved without having > to introduce additional API. > Here is what I came up with to use existing IRQ APIs to implement event mapping. Basically it is the same as my previous suggestion [1], with the addition of multiple IRQ domains. The idea is that each external interrupt controller (or DMA controller, etc.) that is connected to the PRUSS interrupt controller is considered an interrupt domain. One of the objections to my previous patch was that we could only have one IRQ descriptor per event. Now we can have one descriptor per event per domain. I am still proposing that we use the interrupt-cells and identical vendor resource data structures in the PRU firmware be used to provide the mapping information. (As a side note, I still think it is important to include EVTSEL on AM18xx in order to fully describe the event.) The bindings will have N = 4 cells (or N = 5 when EVTSEL is required to fully describe the event): Cell 0: The PRUSS event number, e.g. 0 to 64 for most PRUSSs Cell 1: The EVTSEL value (omitted when N == 4), e.g. 0, 1 or TI_PRUSS_INTC_EVTSEL_ANY if the event is the same for all EVTSEL values. On AM18xx, external events will all require 0 or 1 while system events will always be TI_PRUSS_INTC_EVTSEL_ANY. Cell N-3: The channel that the event gets mapped to, e.g. 0 to 9 Cell N-2: The host that the channel gets mapped to, e.g. 0 to 9 Cell N-1: The interrupt domain, e.g. TI_PRUSS_INTC_DOMAIN_PRU or TI_PRUSS_INTC_DOMAIN_MCU The TI_PRUSS_INTC_DOMAIN_* values are just arbitrary numbers assigned to the possible domains. For example, on AM18xx and AM33xx, there are just two domains, the PRU domain for host 0 and host 1 and the MCU domain for host 2 thru 9. Looking at the AM65xx manual, it looks like it would have 4 domains, the PRU domain, the RTU PRU domain, the MCU domain and a task manager domain. (And I suppose that domains could even be more granular if needed, e.g. we could drop the arbitrary domain number and treat each host interrupt/event as an interrupt domain, then there would be an IRQ descriptor per PRU INTC event per host.) The AM18xx example I have been using will look like this in the device tree: interrupts = <63 TI_PRUSS_INTC_EVTSEL_ANY 0 0 TI_PRUSS_INTC_DOMAIN_PRU>, <62 TI_PRUSS_INTC_EVTSEL_ANY 2 2 TI_PRUSS_INTC_DOMAIN_MCU>; To keep parsing simple, the PRU firmware can include vendor resources that have essentially the same format as the device tree bindings. For example: enum { /* IRQ descriptor without EVTSEL */ TI_PRU_VENDOR_RESOURCE_IRQ = RSC_VENDOR_START, /* IRQ descriptor with EVTSEL */ TI_PRU_VENDOR_RESOURCE_IRQ2, }; struct ti_pru_vendor_resource_irq { __le32 event; __le32 channel; __le32 host; __le32 domain; }; struct ti_pru_vendor_resource_irq2 { __le32 event; __le32 evt_sel; __le32 channel; __le32 host; __le32 domain; }; Then we can provide a vendor resource hook in the remoteproc driver to handle these resources: static int ti_pru_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type, void *rsc, int offset, int avail) { struct ti_pru_data *pru = rproc->priv; struct irq_fwspec fwspec; unsigned int virq; switch (rsc_type) { case TI_PRU_VENDOR_RESOURCE_IRQ: { struct ti_pru_vendor_resource_irq *rsc_irq = rsc; fwspec.fwnode = pru->intc_fwnode; fwspec.param[0] = le32_to_cpu(rsc_irq->event); fwspec.param[1] = le32_to_cpu(rsc_irq->channel); fwspec.param[2] = le32_to_cpu(rsc_irq->host); fwspec.param[3] = le32_to_cpu(rsc_irq->domain); fwspec.param_count = 4; } break; case TI_PRU_VENDOR_RESOURCE_IRQ2: { struct ti_pru_vendor_resource_irq2 *rsc_irq2 = rsc; fwspec.fwnode = pru->intc_fwnode; fwspec.param[0] = le32_to_cpu(rsc_irq2->event); fwspec.param[1] = le32_to_cpu(rsc_irq2->evt_sel); fwspec.param[2] = le32_to_cpu(rsc_irq2->channel); fwspec.param[3] = le32_to_cpu(rsc_irq2->host); fwspec.param[4] = le32_to_cpu(rsc_irq2->domain); fwspec.param_count = 5; break; } default: return RSC_IGNORED; } virq = irq_create_fwspec_mapping(&fwspec); if (!virq) return -EINVAL; /* TODO: save virq (and other metadata) for later use */ return RSC_HANDLED; } static const struct rproc_ops ti_pru_rproc_ops = { .start = ti_pru_rproc_start, .stop = ti_pru_rproc_stop, .kick = ti_pru_rproc_kick, .da_to_va = ti_pru_rproc_da_to_va, .handle_rsc = ti_pru_rproc_handle_rsc, }; The handle_rsc callback is called for each resource when the PRU is booted. The function irq_create_fwspec_mapping() causes the IRQ to be mapped in hardware. From what I understand from the previous discussions, this is exactly when we want this to happen. This patch applies on top of "irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts", "irqchip/irq-pruss-intc: Add support for shared and invalid interrupts" and "irqchip/irq-pruss-intc: Implement irq_{get,set} _irqchip_state ops" from [PATCH v2 0/6] "Add TI PRUSS Local Interrupt Controller IRQChip driver" [2]. A working copy along with some remoteproc and rpmsg hacks can be found on my GitHub [3]. [1]: https://lore.kernel.org/lkml/fb2bdb7b-4d4d-508f-722a-554888280145@lechnology.com/ [2]: https://lore.kernel.org/lkml/20190731224149.11153-1-s-anna@ti.com/ [3]: https://github.com/dlech/linux/commits/pruss-2019-08-08 Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: David Lechner <david@lechnology.com> --- drivers/irqchip/irq-pruss-intc.c | 387 +++++++++++++++++- .../interrupt-controller/ti-pruss.h | 27 ++ 2 files changed, 396 insertions(+), 18 deletions(-) create mode 100644 include/dt-bindings/interrupt-controller/ti-pruss.h diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index c1fd6c09f2f2..da4349df08c3 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -5,6 +5,8 @@ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ * Andrew F. Davis <afd@ti.com> * Suman Anna <s-anna@ti.com> + * + * Copyright (C) 2019 David Lechner <david@lechnology.com> */ #include <linux/interrupt.h> @@ -14,6 +16,14 @@ #include <linux/module.h> #include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/pm_runtime.h> + +#include <dt-bindings/interrupt-controller/ti-pruss.h> + +/* The number of possible interrupt domains, see TI_PRUSS_INTC_DOMAIN_* in + * dt-bindings/interrupt-controller/ti-pruss.h + */ +#define NUM_TI_PRUSS_INTC_DOMAIN 5 /* * Number of host interrupts reaching the main MPU sub-system. Note that this @@ -25,6 +35,12 @@ /* minimum starting host interrupt number for MPU */ #define MIN_PRU_HOST_INT 2 +/* maximum number of host interrupts */ +#define MAX_PRU_HOST_INT 10 + +/* maximum number of interrupt channels */ +#define MAX_PRU_CHANNELS 10 + /* maximum number of system events */ #define MAX_PRU_SYS_EVENTS 64 @@ -57,27 +73,83 @@ #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) #define PRU_INTC_HIER 0x1500 +/* CMR register bit-field macros */ +#define CMR_EVT_MAP_MASK 0xf +#define CMR_EVT_MAP_BITS 8 +#define CMR_EVT_PER_REG 4 + +/* HMR register bit-field macros */ +#define HMR_CH_MAP_MASK 0xf +#define HMR_CH_MAP_BITS 8 +#define HMR_CH_PER_REG 4 + /* HIPIR register bit-fields */ #define INTC_HIPIR_NONE_HINT 0x80000000 +/** + * struct pruss_intc_hwirq_data - additional metadata associated with a PRU + * system event + * @evtsel: The event select index (AM18xx only) + * @channel: The PRU INTC channel that the system event should be mapped to + * @host: The PRU INTC host that the channel should be mapped to + */ +struct pruss_intc_hwirq_data { + u8 evtsel; + u8 channel; + u8 host; +}; + +/** + * struct pruss_intc_map_record - keeps track of actual mapping state + * @value: The currently mapped value (evtsel, channel or host) + * @ref_count: Keeps track of number of current users of this resource + */ +struct pruss_intc_map_record { + u8 value; + u8 ref_count; +}; + +/** + * struct pruss_intc_domain - information specific to an external IRQ domain + * @hwirq_data: Table of additional mapping data received from device tree + * or PRU firmware + * @domain: irq domain + * @intc: the interrupt controller + * @id: Unique domain identifier (from device tree bindings) + */ +struct pruss_intc_domain { + struct pruss_intc_hwirq_data hwirq_data[MAX_PRU_SYS_EVENTS]; + struct irq_domain *domain; + struct pruss_intc *intc; + u32 id; +}; + /** * struct pruss_intc - PRUSS interrupt controller structure + * @domain: External interrupt domains + * @evtsel: Tracks the current state of CFGCHIP3[3].PRUSSEVTSEL (AM18xx only) + * @event_channel: Tracks the current state of system event to channel mappings + * @channel_host: Tracks the current state of channel to host mappings * @irqs: kernel irq numbers corresponding to PRUSS host interrupts * @base: base virtual address of INTC register space * @irqchip: irq chip for this interrupt controller - * @domain: irq domain for this interrupt controller * @lock: mutex to serialize access to INTC * @shared_intr: bit-map denoting if the MPU host interrupt is shared * @invalid_intr: bit-map denoting if host interrupt is not connected to MPU + * @has_evtsel: indicates that the chip has an event select mux */ struct pruss_intc { + struct pruss_intc_domain domain[NUM_ISA_INTERRUPTS]; + struct pruss_intc_map_record evtsel; + struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS]; + struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS]; unsigned int irqs[MAX_NUM_HOST_IRQS]; void __iomem *base; struct irq_chip *irqchip; - struct irq_domain *domain; struct mutex lock; /* PRUSS INTC lock */ u16 shared_intr; u16 invalid_intr; + bool has_evtsel; }; static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) @@ -105,6 +177,172 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, return 0; } +/** + * pruss_intc_map() - configure the PRUSS INTC + * @domain: pru intc domain pointer + * @hwirq: the system event number + * + * Configures the PRUSS INTC with the provided configuration from the one + * parsed in the xlate function. Any existing event to channel mappings or + * channel to host interrupt mappings are checked to make sure there are no + * conflicting configuration between both the PRU cores. + * + * Returns 0 on success, or a suitable error code otherwise + */ +static int pruss_intc_map(struct pruss_intc_domain *domain, unsigned long hwirq) +{ + struct pruss_intc *intc = domain->intc; + struct device* dev = intc->irqchip->parent_device; + u32 val; + int idx, ret; + u8 evtsel, ch, host; + + if (hwirq >= MAX_PRU_SYS_EVENTS) + return -EINVAL; + + mutex_lock(&intc->lock); + + evtsel = domain->hwirq_data[hwirq].evtsel; + ch = domain->hwirq_data[hwirq].channel; + host = domain->hwirq_data[hwirq].host; + + if (intc->has_evtsel && intc->evtsel.ref_count > 0 && + intc->evtsel.value != evtsel) { + dev_err(dev, "event %lu (req. evtsel %d) already assigned to evtsel %d\n", + hwirq, evtsel, intc->evtsel.value); + ret = -EBUSY; + goto unlock; + } + + /* check if sysevent already assigned */ + if (intc->event_channel[hwirq].ref_count > 0 && + intc->event_channel[hwirq].value != ch) { + dev_err(dev, "event %lu (req. channel %d) already assigned to channel %d\n", + hwirq, ch, intc->event_channel[hwirq].value); + ret = -EBUSY; + goto unlock; + } + + /* check if channel already assigned */ + if (intc->channel_host[ch].ref_count > 0 && + intc->channel_host[ch].value != host) { + dev_err(dev, "channel %d (req. host %d) already assigned to host %d\n", + ch, host, intc->channel_host[ch].value); + ret = -EBUSY; + goto unlock; + } + + if (++intc->evtsel.ref_count == 1) { + intc->evtsel.value = evtsel; + + /* TODO: need to implement CFGCHIP3[3].PRUSSEVTSEL */ + } + + if (++intc->event_channel[hwirq].ref_count == 1) { + intc->event_channel[hwirq].value = ch; + + /* + * configure channel map registers - each register holds map + * info for 4 events, with each event occupying the lower nibble + * in a register byte address in little-endian fashion + */ + idx = hwirq / CMR_EVT_PER_REG; + + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); + val &= ~(CMR_EVT_MAP_MASK << + ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS)); + val |= ch << ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS); + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); + + dev_dbg(dev, "SYSEV%lu -> CH%d (CMR%d 0x%08x)\n", hwirq, ch, + idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); + + /* clear and enable system event */ + pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq); + pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq); + } + + if (++intc->channel_host[ch].ref_count == 1) { + intc->channel_host[ch].value = host; + + /* + * set host map registers - each register holds map info for + * 4 channels, with each channel occupying the lower nibble in + * a register byte address in little-endian fashion + */ + idx = ch / HMR_CH_PER_REG; + + val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)); + val &= ~(HMR_CH_MAP_MASK << + ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS)); + val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS); + pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val); + + dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx, + pruss_intc_read_reg(intc, PRU_INTC_HMR(idx))); + + /* enable host interrupts */ + pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host); + } + + dev_info(dev, "mapped system_event = %lu channel = %d host = %d domain = %u\n", + hwirq, ch, host, domain->id); + + /* global interrupt enable */ + pruss_intc_write_reg(intc, PRU_INTC_GER, 1); + + mutex_unlock(&intc->lock); + return 0; + +unlock: + mutex_unlock(&intc->lock); + return ret; +} + +/** + * pruss_intc_unmap() - unconfigure the PRUSS INTC + * @domain: pru intc domain pointer + * @hwirq: the system event number + * + * Undo whatever was done in pruss_intc_map() for a PRU core. + * Mappings are reference counted, so resources are only disabled when there + * are no longer any users. + */ +static void pruss_intc_unmap(struct pruss_intc_domain *domain, unsigned long hwirq) +{ + struct pruss_intc *intc = domain->intc; + struct device* dev = intc->irqchip->parent_device; + u8 ch, host; + + if (hwirq >= MAX_PRU_SYS_EVENTS) + return; + + mutex_lock(&intc->lock); + + ch = intc->event_channel[hwirq].value; + host = intc->channel_host[ch].value; + + if (--intc->channel_host[ch].ref_count == 0) { + /* disable host interrupts */ + pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host); + } + + if (--intc->event_channel[hwirq].ref_count == 0) { + /* disable system events */ + pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq); + /* clear any pending status */ + pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq); + } + + if (intc->has_evtsel) + intc->evtsel.ref_count--; + + dev_info(dev, "unmapped system_event = %lu channel = %d host = %d\n", + hwirq, ch, host); + + mutex_unlock(&intc->lock); +} + static void pruss_intc_init(struct pruss_intc *intc) { int i; @@ -198,10 +436,83 @@ static int pruss_intc_irq_set_irqchip_state(struct irq_data *data, return pruss_intc_check_write(intc, PRU_INTC_SICR, data->hwirq); } +static int pruss_intc_irq_domain_select(struct irq_domain *d, + struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token) +{ + struct pruss_intc_domain *domain = d->host_data; + int num_cells = domain->intc->has_evtsel ? 5 : 4; + u32 domain_id; + + if (!fwspec || fwspec->fwnode != domain->domain->fwnode) + return 0; + + if (bus_token != DOMAIN_BUS_ANY && bus_token != domain->domain->bus_token) + return 0; + + if (WARN_ON_ONCE(fwspec->param_count != num_cells)) + return 0; + + domain_id = fwspec->param[fwspec->param_count - 1]; + if (domain_id != domain->id) + return 0; + + return 1; +} + +static int +pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node *node, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, unsigned int *out_type) +{ + struct pruss_intc_domain *domain = d->host_data; + struct pruss_intc *intc = domain->intc; + int num_cells = intc->has_evtsel ? 5 : 4; + u32 sys_event, channel, host, domain_id; + u32 evtsel = 0; + + if (WARN_ON_ONCE(intsize != num_cells)) + return -EINVAL; + + sys_event = intspec[0]; + if (sys_event >= MAX_PRU_SYS_EVENTS) + return -EINVAL; + + if (intc->has_evtsel) + evtsel = intspec[1]; + + channel = intspec[intsize - 3]; + if (channel >= MAX_PRU_CHANNELS) + return -EINVAL; + + host = intspec[intsize - 2]; + if (host >= MAX_PRU_HOST_INT) + return -EINVAL; + + domain_id = intspec[intsize - 1]; + if (domain_id != domain->id) + return -EINVAL; + + domain->hwirq_data[sys_event].evtsel = evtsel; + domain->hwirq_data[sys_event].channel = channel; + domain->hwirq_data[sys_event].host = host; + + *out_hwirq = sys_event; + *out_type = IRQ_TYPE_NONE; + + return 0; +} + static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw) { - struct pruss_intc *intc = d->host_data; + struct pruss_intc_domain *domain = d->host_data; + struct pruss_intc *intc = domain->intc; + int err; + + err = pruss_intc_map(domain, hw); + if (err < 0) + return err; irq_set_chip_data(virq, intc); irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq); @@ -211,12 +522,17 @@ static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq) { + struct pruss_intc_domain *domain = d->host_data; + unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq)); + irq_set_chip_and_handler(virq, NULL, NULL); irq_set_chip_data(virq, NULL); + pruss_intc_unmap(domain, hwirq); } static const struct irq_domain_ops pruss_intc_irq_domain_ops = { - .xlate = irq_domain_xlate_onecell, + .select = pruss_intc_irq_domain_select, + .xlate = pruss_intc_irq_domain_xlate, .map = pruss_intc_irq_domain_map, .unmap = pruss_intc_irq_domain_unmap, }; @@ -245,7 +561,8 @@ static void pruss_intc_irq_handler(struct irq_desc *desc) hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); while (!(hipir & INTC_HIPIR_NONE_HINT)) { hwirq = hipir & GENMASK(9, 0); - virq = irq_linear_revmap(intc->domain, hwirq); + virq = irq_linear_revmap( + intc->domain[TI_PRUSS_INTC_DOMAIN_MCU].domain, hwirq); /* * NOTE: manually ACK any system events that do not have a @@ -272,7 +589,8 @@ static int pruss_intc_probe(struct platform_device *pdev) struct pruss_intc *intc; struct resource *res; struct irq_chip *irqchip; - int i, irq, count; + int i, err, irq, count; + u32 num_cells; u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 }; intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); @@ -323,13 +641,22 @@ static int pruss_intc_probe(struct platform_device *pdev) } } + err = of_property_read_u32(dev->of_node, "#interrupt-cells", &num_cells); + if (!err && num_cells == 5) + intc->has_evtsel = true; + mutex_init(&intc->lock); + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + pruss_intc_init(intc); irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); - if (!irqchip) - return -ENOMEM; + if (!irqchip) { + err = -ENOMEM; + goto fail_alloc; + } irqchip->irq_ack = pruss_intc_irq_ack; irqchip->irq_mask = pruss_intc_irq_mask; @@ -338,14 +665,24 @@ static int pruss_intc_probe(struct platform_device *pdev) irqchip->irq_release_resources = pruss_intc_irq_relres; irqchip->irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state; irqchip->irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state; + irqchip->parent_device = dev; irqchip->name = dev_name(dev); intc->irqchip = irqchip; - /* always 64 events */ - intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS, - &pruss_intc_irq_domain_ops, intc); - if (!intc->domain) - return -ENOMEM; + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) { + intc->domain[i].intc = intc; + intc->domain[i].id = i; + /* always 64 events */ + intc->domain[i].domain = irq_domain_add_linear(dev->of_node, + MAX_PRU_SYS_EVENTS, &pruss_intc_irq_domain_ops, + &intc->domain[i]); + if (!intc->domain[i].domain) { + while (--i >= 0) + irq_domain_remove(intc->domain[i].domain); + err = -ENOMEM; + goto fail_alloc; + } + } for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { irq = platform_get_irq_byname(pdev, irq_names[i]); @@ -356,6 +693,7 @@ static int pruss_intc_probe(struct platform_device *pdev) dev_err(dev, "platform_get_irq_byname failed for %s : %d\n", irq_names[i], irq); + err = irq; goto fail_irq; } @@ -372,13 +710,20 @@ static int pruss_intc_probe(struct platform_device *pdev) irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); } - irq_domain_remove(intc->domain); - return irq; + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) + irq_domain_remove(intc->domain[i].domain); + +fail_alloc: + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return err; } static int pruss_intc_remove(struct platform_device *pdev) { struct pruss_intc *intc = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; unsigned int hwirq; int i; @@ -388,9 +733,15 @@ static int pruss_intc_remove(struct platform_device *pdev) NULL); } - for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) - irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); - irq_domain_remove(intc->domain); + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) { + for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) + irq_dispose_mapping(irq_find_mapping( + intc->domain[i].domain, hwirq)); + irq_domain_remove(intc->domain[i].domain); + } + + pm_runtime_put(dev); + pm_runtime_disable(dev); return 0; } diff --git a/include/dt-bindings/interrupt-controller/ti-pruss.h b/include/dt-bindings/interrupt-controller/ti-pruss.h new file mode 100644 index 000000000000..326a68c31bce --- /dev/null +++ b/include/dt-bindings/interrupt-controller/ti-pruss.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * This header provides constants for the Texas Instruments Programmable + * Realtime Unit Subsystem (PRUSS) interrupt controller. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H + +/* interrupt specifier for optional cell 1 */ + +#define TI_PRUSS_INTC_EVTSEL_ANY 0xffffffff + +/* interrupt specifier for cell #interrupt-cells - 1 */ + +/* host interrupt is connected to PRU cores, e.g. host events 0 and 1 */ +#define TI_PRUSS_INTC_DOMAIN_PRU 0 +/* host interrupt is connected to MCU's interrupt controller */ +#define TI_PRUSS_INTC_DOMAIN_MCU 1 +/* host interrupt is connected to DSP's interrupt controller */ +#define TI_PRUSS_INTC_DOMAIN_DSP 2 +/* host interrupt is connected to the auxillary PRU cores */ +#define TI_PRUSS_INTC_DOMAIN_RTU_PRU 3 +/* host interrupt is connected to the task managers */ +#define TI_PRUSS_INTC_DOMAIN_TASK 4 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H */
On 8/8/19 12:09 PM, David Lechner wrote: > > Then we can provide a vendor resource hook in the remoteproc driver to handle > these resources: > > static int ti_pru_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type, void *rsc, > int offset, int avail) > { > struct ti_pru_data *pru = rproc->priv; > struct irq_fwspec fwspec; > unsigned int virq; > > switch (rsc_type) { > case TI_PRU_VENDOR_RESOURCE_IRQ: > { > struct ti_pru_vendor_resource_irq *rsc_irq = rsc; > > fwspec.fwnode = pru->intc_fwnode; > fwspec.param[0] = le32_to_cpu(rsc_irq->event); > fwspec.param[1] = le32_to_cpu(rsc_irq->channel); > fwspec.param[2] = le32_to_cpu(rsc_irq->host); > fwspec.param[3] = le32_to_cpu(rsc_irq->domain); > fwspec.param_count = 4; > } > break; > case TI_PRU_VENDOR_RESOURCE_IRQ2: > { > struct ti_pru_vendor_resource_irq2 *rsc_irq2 = rsc; > > fwspec.fwnode = pru->intc_fwnode; > fwspec.param[0] = le32_to_cpu(rsc_irq2->event); > fwspec.param[1] = le32_to_cpu(rsc_irq2->evt_sel); > fwspec.param[2] = le32_to_cpu(rsc_irq2->channel); > fwspec.param[3] = le32_to_cpu(rsc_irq2->host); > fwspec.param[4] = le32_to_cpu(rsc_irq2->domain); > fwspec.param_count = 5; > break; > } > default: > return RSC_IGNORED; > } > > virq = irq_create_fwspec_mapping(&fwspec); > if (!virq) > return -EINVAL; > > /* TODO: save virq (and other metadata) for later use */ > > return RSC_HANDLED; > } > > static const struct rproc_ops ti_pru_rproc_ops = { > .start = ti_pru_rproc_start, > .stop = ti_pru_rproc_stop, > .kick = ti_pru_rproc_kick, > .da_to_va = ti_pru_rproc_da_to_va, > .handle_rsc = ti_pru_rproc_handle_rsc, > }; > After re-reading some of the previous discussions, it sounds like we wouldn't want to always map every IRQ in the firmware resource table. In that case, we could implement the rproc_ops parse_fw callback instead. All firmware nodes could be collected (from both the firmware resource table and device tree) and the remoteproc driver could decide which ones need to be mapped and which ones don't. Then it could call irq_create_fwspec_mapping() only the nodes that need to be mapped based on the current application.
Hi David, On 8/8/19 12:09 PM, David Lechner wrote: > On 8/2/19 4:26 PM, Suman Anna wrote: >> Point is different applications might use mapping differently as per >> their firmware and driver/application design and their split across one >> or more PRUs (design by contract). And we need to set this up at runtime >> when the application driver is getting run. We will have either the Soft >> UART or the Ethernet running at a time depending on the end goal desired >> >>> I have an idea that we can use multiple struct irq_domains to make >>> this work in the existing IRQ framework, but it would be helpful to >>> know more about the bigger picture first. >> >> Yeah, would be great if there is a way this can be solved without having >> to introduce additional API. >> > > > Here is what I came up with to use existing IRQ APIs to implement event > mapping. > Basically it is the same as my previous suggestion [1], with the > addition of > multiple IRQ domains. First of all, many thanks for looking into the problem and providing patches for the alternate solutions. If we were to not use any exported functions, this approach does seem to be a viable solution. I am going to play around with both [1] and this patch with all our existing usecases and see if I run into any issues. So, w.r.t this patch compared to [1], is the multiple IRQ domain solving anything specifically? Our main issue is the re-purposing of a event (and its mapping depending on the application), and the same issue will remain whether we have multiple domains or not. Also, now we would expect an event to migrate between different domains based on its usage. > > The idea is that each external interrupt controller (or DMA controller, > etc.) > that is connected to the PRUSS interrupt controller is considered an > interrupt > domain. One of the objections to my previous patch was that we could > only have > one IRQ descriptor per event. Now we can have one descriptor per event per > domain. > > I am still proposing that we use the interrupt-cells and identical vendor > resource data structures in the PRU firmware be used to provide the mapping > information. (As a side note, I still think it is important to include > EVTSEL > on AM18xx in order to fully describe the event.) W.r.t EVTSEL, it is a global value and applies to a range of events. I have another equivalent register/functionality on most of the other SoCs as well (a register in PRUSS_CFG space) that muxes standard events vs MII_RT events. Again, that is limited to only a subset of all the system events. So, should this continue to be a per event specifier, it will be yet another mapping configuration data item (my idea was to manage this once per application within the PRU remoteproc driver along with the fwspec mapping). regards Suman > > The bindings will have N = 4 cells (or N = 5 when EVTSEL is required to > fully > describe the event): > > Cell 0: The PRUSS event number, e.g. 0 to 64 for most PRUSSs > Cell 1: The EVTSEL value (omitted when N == 4), e.g. 0, 1 or > TI_PRUSS_INTC_EVTSEL_ANY if the event is the same for all EVTSEL > values. On AM18xx, external events will all require 0 or 1 while > system events will always be TI_PRUSS_INTC_EVTSEL_ANY. > Cell N-3: The channel that the event gets mapped to, e.g. 0 to 9 > Cell N-2: The host that the channel gets mapped to, e.g. 0 to 9 > Cell N-1: The interrupt domain, e.g. TI_PRUSS_INTC_DOMAIN_PRU or > TI_PRUSS_INTC_DOMAIN_MCU > > The TI_PRUSS_INTC_DOMAIN_* values are just arbitrary numbers assigned to > the > possible domains. For example, on AM18xx and AM33xx, there are just two > domains, > the PRU domain for host 0 and host 1 and the MCU domain for host 2 thru 9. > Looking at the AM65xx manual, it looks like it would have 4 domains, the > PRU > domain, the RTU PRU domain, the MCU domain and a task manager domain. > (And I > suppose that domains could even be more granular if needed, e.g. we > could drop > the arbitrary domain number and treat each host interrupt/event as an > interrupt > domain, then there would be an IRQ descriptor per PRU INTC event per host.) > > The AM18xx example I have been using will look like this in the device > tree: > > interrupts = <63 TI_PRUSS_INTC_EVTSEL_ANY 0 0 > TI_PRUSS_INTC_DOMAIN_PRU>, > <62 TI_PRUSS_INTC_EVTSEL_ANY 2 2 TI_PRUSS_INTC_DOMAIN_MCU>; > > To keep parsing simple, the PRU firmware can include vendor resources > that have > essentially the same format as the device tree bindings. For example: > > enum { > /* IRQ descriptor without EVTSEL */ > TI_PRU_VENDOR_RESOURCE_IRQ = RSC_VENDOR_START, > /* IRQ descriptor with EVTSEL */ > TI_PRU_VENDOR_RESOURCE_IRQ2, > }; > > struct ti_pru_vendor_resource_irq { > __le32 event; > __le32 channel; > __le32 host; > __le32 domain; > }; > > struct ti_pru_vendor_resource_irq2 { > __le32 event; > __le32 evt_sel; > __le32 channel; > __le32 host; > __le32 domain; > }; > > Then we can provide a vendor resource hook in the remoteproc driver to > handle > these resources: > > static int ti_pru_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type, > void *rsc, > int offset, int avail) > { > struct ti_pru_data *pru = rproc->priv; > struct irq_fwspec fwspec; > unsigned int virq; > > switch (rsc_type) { > case TI_PRU_VENDOR_RESOURCE_IRQ: > { > struct ti_pru_vendor_resource_irq *rsc_irq = rsc; > > fwspec.fwnode = pru->intc_fwnode; > fwspec.param[0] = le32_to_cpu(rsc_irq->event); > fwspec.param[1] = le32_to_cpu(rsc_irq->channel); > fwspec.param[2] = le32_to_cpu(rsc_irq->host); > fwspec.param[3] = le32_to_cpu(rsc_irq->domain); > fwspec.param_count = 4; > } > break; > case TI_PRU_VENDOR_RESOURCE_IRQ2: > { > struct ti_pru_vendor_resource_irq2 *rsc_irq2 = rsc; > > fwspec.fwnode = pru->intc_fwnode; > fwspec.param[0] = le32_to_cpu(rsc_irq2->event); > fwspec.param[1] = le32_to_cpu(rsc_irq2->evt_sel); > fwspec.param[2] = le32_to_cpu(rsc_irq2->channel); > fwspec.param[3] = le32_to_cpu(rsc_irq2->host); > fwspec.param[4] = le32_to_cpu(rsc_irq2->domain); > fwspec.param_count = 5; > break; > } > default: > return RSC_IGNORED; > } > > virq = irq_create_fwspec_mapping(&fwspec); > if (!virq) > return -EINVAL; > > /* TODO: save virq (and other metadata) for later use */ > > return RSC_HANDLED; > } > > static const struct rproc_ops ti_pru_rproc_ops = { > .start = ti_pru_rproc_start, > .stop = ti_pru_rproc_stop, > .kick = ti_pru_rproc_kick, > .da_to_va = ti_pru_rproc_da_to_va, > .handle_rsc = ti_pru_rproc_handle_rsc, > }; > > The handle_rsc callback is called for each resource when the PRU is booted. > The function irq_create_fwspec_mapping() causes the IRQ to be mapped in > hardware. From what I understand from the previous discussions, this is > exactly > when we want this to happen. > > This patch applies on top of "irqchip/irq-pruss-intc: Add a PRUSS > irqchip driver > for PRUSS interrupts", "irqchip/irq-pruss-intc: Add support for shared and > invalid interrupts" and "irqchip/irq-pruss-intc: Implement irq_{get,set} > _irqchip_state ops" from [PATCH v2 0/6] "Add TI PRUSS Local Interrupt > Controller > IRQChip driver" [2]. > > A working copy along with some remoteproc and rpmsg hacks can be found > on my > GitHub [3]. > > [1]: > https://lore.kernel.org/lkml/fb2bdb7b-4d4d-508f-722a-554888280145@lechnology.com/ > > [2]: https://lore.kernel.org/lkml/20190731224149.11153-1-s-anna@ti.com/ > [3]: https://github.com/dlech/linux/commits/pruss-2019-08-08 > > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Andrew F. Davis <afd@ti.com> > Signed-off-by: Roger Quadros <rogerq@ti.com> > Signed-off-by: David Lechner <david@lechnology.com> > --- > drivers/irqchip/irq-pruss-intc.c | 387 +++++++++++++++++- > .../interrupt-controller/ti-pruss.h | 27 ++ > 2 files changed, 396 insertions(+), 18 deletions(-) > create mode 100644 include/dt-bindings/interrupt-controller/ti-pruss.h > > diff --git a/drivers/irqchip/irq-pruss-intc.c > b/drivers/irqchip/irq-pruss-intc.c > index c1fd6c09f2f2..da4349df08c3 100644 > --- a/drivers/irqchip/irq-pruss-intc.c > +++ b/drivers/irqchip/irq-pruss-intc.c > @@ -5,6 +5,8 @@ > * Copyright (C) 2016-2019 Texas Instruments Incorporated - > http://www.ti.com/ > * Andrew F. Davis <afd@ti.com> > * Suman Anna <s-anna@ti.com> > + * > + * Copyright (C) 2019 David Lechner <david@lechnology.com> > */ > > #include <linux/interrupt.h> > @@ -14,6 +16,14 @@ > #include <linux/module.h> > #include <linux/of_device.h> > #include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > + > +#include <dt-bindings/interrupt-controller/ti-pruss.h> > + > +/* The number of possible interrupt domains, see TI_PRUSS_INTC_DOMAIN_* in > + * dt-bindings/interrupt-controller/ti-pruss.h > + */ > +#define NUM_TI_PRUSS_INTC_DOMAIN 5 > > /* > * Number of host interrupts reaching the main MPU sub-system. Note > that this > @@ -25,6 +35,12 @@ > /* minimum starting host interrupt number for MPU */ > #define MIN_PRU_HOST_INT 2 > > +/* maximum number of host interrupts */ > +#define MAX_PRU_HOST_INT 10 > + > +/* maximum number of interrupt channels */ > +#define MAX_PRU_CHANNELS 10 > + > /* maximum number of system events */ > #define MAX_PRU_SYS_EVENTS 64 > > @@ -57,27 +73,83 @@ > #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) > #define PRU_INTC_HIER 0x1500 > > +/* CMR register bit-field macros */ > +#define CMR_EVT_MAP_MASK 0xf > +#define CMR_EVT_MAP_BITS 8 > +#define CMR_EVT_PER_REG 4 > + > +/* HMR register bit-field macros */ > +#define HMR_CH_MAP_MASK 0xf > +#define HMR_CH_MAP_BITS 8 > +#define HMR_CH_PER_REG 4 > + > /* HIPIR register bit-fields */ > #define INTC_HIPIR_NONE_HINT 0x80000000 > > +/** > + * struct pruss_intc_hwirq_data - additional metadata associated with a > PRU > + * system event > + * @evtsel: The event select index (AM18xx only) > + * @channel: The PRU INTC channel that the system event should be > mapped to > + * @host: The PRU INTC host that the channel should be mapped to > + */ > +struct pruss_intc_hwirq_data { > + u8 evtsel; > + u8 channel; > + u8 host; > +}; > + > +/** > + * struct pruss_intc_map_record - keeps track of actual mapping state > + * @value: The currently mapped value (evtsel, channel or host) > + * @ref_count: Keeps track of number of current users of this resource > + */ > +struct pruss_intc_map_record { > + u8 value; > + u8 ref_count; > +}; > + > +/** > + * struct pruss_intc_domain - information specific to an external IRQ > domain > + * @hwirq_data: Table of additional mapping data received from device tree > + * or PRU firmware > + * @domain: irq domain > + * @intc: the interrupt controller > + * @id: Unique domain identifier (from device tree bindings) > + */ > +struct pruss_intc_domain { > + struct pruss_intc_hwirq_data hwirq_data[MAX_PRU_SYS_EVENTS]; > + struct irq_domain *domain; > + struct pruss_intc *intc; > + u32 id; > +}; > + > /** > * struct pruss_intc - PRUSS interrupt controller structure > + * @domain: External interrupt domains > + * @evtsel: Tracks the current state of CFGCHIP3[3].PRUSSEVTSEL (AM18xx > only) > + * @event_channel: Tracks the current state of system event to channel > mappings > + * @channel_host: Tracks the current state of channel to host mappings > * @irqs: kernel irq numbers corresponding to PRUSS host interrupts > * @base: base virtual address of INTC register space > * @irqchip: irq chip for this interrupt controller > - * @domain: irq domain for this interrupt controller > * @lock: mutex to serialize access to INTC > * @shared_intr: bit-map denoting if the MPU host interrupt is shared > * @invalid_intr: bit-map denoting if host interrupt is not connected > to MPU > + * @has_evtsel: indicates that the chip has an event select mux > */ > struct pruss_intc { > + struct pruss_intc_domain domain[NUM_ISA_INTERRUPTS]; > + struct pruss_intc_map_record evtsel; > + struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS]; > + struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS]; > unsigned int irqs[MAX_NUM_HOST_IRQS]; > void __iomem *base; > struct irq_chip *irqchip; > - struct irq_domain *domain; > struct mutex lock; /* PRUSS INTC lock */ > u16 shared_intr; > u16 invalid_intr; > + bool has_evtsel; > }; > > static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned > int reg) > @@ -105,6 +177,172 @@ static int pruss_intc_check_write(struct > pruss_intc *intc, unsigned int reg, > return 0; > } > > +/** > + * pruss_intc_map() - configure the PRUSS INTC > + * @domain: pru intc domain pointer > + * @hwirq: the system event number > + * > + * Configures the PRUSS INTC with the provided configuration from the one > + * parsed in the xlate function. Any existing event to channel mappings or > + * channel to host interrupt mappings are checked to make sure there > are no > + * conflicting configuration between both the PRU cores. > + * > + * Returns 0 on success, or a suitable error code otherwise > + */ > +static int pruss_intc_map(struct pruss_intc_domain *domain, unsigned > long hwirq) > +{ > + struct pruss_intc *intc = domain->intc; > + struct device* dev = intc->irqchip->parent_device; > + u32 val; > + int idx, ret; > + u8 evtsel, ch, host; > + > + if (hwirq >= MAX_PRU_SYS_EVENTS) > + return -EINVAL; > + > + mutex_lock(&intc->lock); > + > + evtsel = domain->hwirq_data[hwirq].evtsel; > + ch = domain->hwirq_data[hwirq].channel; > + host = domain->hwirq_data[hwirq].host; > + > + if (intc->has_evtsel && intc->evtsel.ref_count > 0 && > + intc->evtsel.value != evtsel) { > + dev_err(dev, "event %lu (req. evtsel %d) already assigned to > evtsel %d\n", > + hwirq, evtsel, intc->evtsel.value); > + ret = -EBUSY; > + goto unlock; > + } > + > + /* check if sysevent already assigned */ > + if (intc->event_channel[hwirq].ref_count > 0 && > + intc->event_channel[hwirq].value != ch) { > + dev_err(dev, "event %lu (req. channel %d) already assigned to > channel %d\n", > + hwirq, ch, intc->event_channel[hwirq].value); > + ret = -EBUSY; > + goto unlock; > + } > + > + /* check if channel already assigned */ > + if (intc->channel_host[ch].ref_count > 0 && > + intc->channel_host[ch].value != host) { > + dev_err(dev, "channel %d (req. host %d) already assigned to > host %d\n", > + ch, host, intc->channel_host[ch].value); > + ret = -EBUSY; > + goto unlock; > + } > + > + if (++intc->evtsel.ref_count == 1) { > + intc->evtsel.value = evtsel; > + > + /* TODO: need to implement CFGCHIP3[3].PRUSSEVTSEL */ > + } > + > + if (++intc->event_channel[hwirq].ref_count == 1) { > + intc->event_channel[hwirq].value = ch; > + > + /* > + * configure channel map registers - each register holds map > + * info for 4 events, with each event occupying the lower nibble > + * in a register byte address in little-endian fashion > + */ > + idx = hwirq / CMR_EVT_PER_REG; > + > + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); > + val &= ~(CMR_EVT_MAP_MASK << > + ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS)); > + val |= ch << ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS); > + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); > + > + dev_dbg(dev, "SYSEV%lu -> CH%d (CMR%d 0x%08x)\n", hwirq, ch, > + idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); > + > + /* clear and enable system event */ > + pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq); > + pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq); > + } > + > + if (++intc->channel_host[ch].ref_count == 1) { > + intc->channel_host[ch].value = host; > + > + /* > + * set host map registers - each register holds map info for > + * 4 channels, with each channel occupying the lower nibble in > + * a register byte address in little-endian fashion > + */ > + idx = ch / HMR_CH_PER_REG; > + > + val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)); > + val &= ~(HMR_CH_MAP_MASK << > + ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS)); > + val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS); > + pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val); > + > + dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx, > + pruss_intc_read_reg(intc, PRU_INTC_HMR(idx))); > + > + /* enable host interrupts */ > + pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host); > + } > + > + dev_info(dev, "mapped system_event = %lu channel = %d host = %d > domain = %u\n", > + hwirq, ch, host, domain->id); > + > + /* global interrupt enable */ > + pruss_intc_write_reg(intc, PRU_INTC_GER, 1); > + > + mutex_unlock(&intc->lock); > + return 0; > + > +unlock: > + mutex_unlock(&intc->lock); > + return ret; > +} > + > +/** > + * pruss_intc_unmap() - unconfigure the PRUSS INTC > + * @domain: pru intc domain pointer > + * @hwirq: the system event number > + * > + * Undo whatever was done in pruss_intc_map() for a PRU core. > + * Mappings are reference counted, so resources are only disabled when > there > + * are no longer any users. > + */ > +static void pruss_intc_unmap(struct pruss_intc_domain *domain, unsigned > long hwirq) > +{ > + struct pruss_intc *intc = domain->intc; > + struct device* dev = intc->irqchip->parent_device; > + u8 ch, host; > + > + if (hwirq >= MAX_PRU_SYS_EVENTS) > + return; > + > + mutex_lock(&intc->lock); > + > + ch = intc->event_channel[hwirq].value; > + host = intc->channel_host[ch].value; > + > + if (--intc->channel_host[ch].ref_count == 0) { > + /* disable host interrupts */ > + pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host); > + } > + > + if (--intc->event_channel[hwirq].ref_count == 0) { > + /* disable system events */ > + pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq); > + /* clear any pending status */ > + pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq); > + } > + > + if (intc->has_evtsel) > + intc->evtsel.ref_count--; > + > + dev_info(dev, "unmapped system_event = %lu channel = %d host = %d\n", > + hwirq, ch, host); > + > + mutex_unlock(&intc->lock); > +} > + > static void pruss_intc_init(struct pruss_intc *intc) > { > int i; > @@ -198,10 +436,83 @@ static int pruss_intc_irq_set_irqchip_state(struct > irq_data *data, > return pruss_intc_check_write(intc, PRU_INTC_SICR, data->hwirq); > } > > +static int pruss_intc_irq_domain_select(struct irq_domain *d, > + struct irq_fwspec *fwspec, > + enum irq_domain_bus_token bus_token) > +{ > + struct pruss_intc_domain *domain = d->host_data; > + int num_cells = domain->intc->has_evtsel ? 5 : 4; > + u32 domain_id; > + > + if (!fwspec || fwspec->fwnode != domain->domain->fwnode) > + return 0; > + > + if (bus_token != DOMAIN_BUS_ANY && bus_token != > domain->domain->bus_token) > + return 0; > + > + if (WARN_ON_ONCE(fwspec->param_count != num_cells)) > + return 0; > + > + domain_id = fwspec->param[fwspec->param_count - 1]; > + if (domain_id != domain->id) > + return 0; > + > + return 1; > +} > + > +static int > +pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node > *node, > + const u32 *intspec, unsigned int intsize, > + unsigned long *out_hwirq, unsigned int *out_type) > +{ > + struct pruss_intc_domain *domain = d->host_data; > + struct pruss_intc *intc = domain->intc; > + int num_cells = intc->has_evtsel ? 5 : 4; > + u32 sys_event, channel, host, domain_id; > + u32 evtsel = 0; > + > + if (WARN_ON_ONCE(intsize != num_cells)) > + return -EINVAL; > + > + sys_event = intspec[0]; > + if (sys_event >= MAX_PRU_SYS_EVENTS) > + return -EINVAL; > + > + if (intc->has_evtsel) > + evtsel = intspec[1]; > + > + channel = intspec[intsize - 3]; > + if (channel >= MAX_PRU_CHANNELS) > + return -EINVAL; > + > + host = intspec[intsize - 2]; > + if (host >= MAX_PRU_HOST_INT) > + return -EINVAL; > + > + domain_id = intspec[intsize - 1]; > + if (domain_id != domain->id) > + return -EINVAL; > + > + domain->hwirq_data[sys_event].evtsel = evtsel; > + domain->hwirq_data[sys_event].channel = channel; > + domain->hwirq_data[sys_event].host = host; > + > + *out_hwirq = sys_event; > + *out_type = IRQ_TYPE_NONE; > + > + return 0; > +} > + > static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int > virq, > irq_hw_number_t hw) > { > - struct pruss_intc *intc = d->host_data; > + struct pruss_intc_domain *domain = d->host_data; > + struct pruss_intc *intc = domain->intc; > + int err; > + > + err = pruss_intc_map(domain, hw); > + if (err < 0) > + return err; > > irq_set_chip_data(virq, intc); > irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq); > @@ -211,12 +522,17 @@ static int pruss_intc_irq_domain_map(struct > irq_domain *d, unsigned int virq, > > static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned > int virq) > { > + struct pruss_intc_domain *domain = d->host_data; > + unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq)); > + > irq_set_chip_and_handler(virq, NULL, NULL); > irq_set_chip_data(virq, NULL); > + pruss_intc_unmap(domain, hwirq); > } > > static const struct irq_domain_ops pruss_intc_irq_domain_ops = { > - .xlate = irq_domain_xlate_onecell, > + .select = pruss_intc_irq_domain_select, > + .xlate = pruss_intc_irq_domain_xlate, > .map = pruss_intc_irq_domain_map, > .unmap = pruss_intc_irq_domain_unmap, > }; > @@ -245,7 +561,8 @@ static void pruss_intc_irq_handler(struct irq_desc > *desc) > hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); > while (!(hipir & INTC_HIPIR_NONE_HINT)) { > hwirq = hipir & GENMASK(9, 0); > - virq = irq_linear_revmap(intc->domain, hwirq); > + virq = irq_linear_revmap( > + intc->domain[TI_PRUSS_INTC_DOMAIN_MCU].domain, hwirq); > > /* > * NOTE: manually ACK any system events that do not have a > @@ -272,7 +589,8 @@ static int pruss_intc_probe(struct platform_device > *pdev) > struct pruss_intc *intc; > struct resource *res; > struct irq_chip *irqchip; > - int i, irq, count; > + int i, err, irq, count; > + u32 num_cells; > u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 }; > > intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); > @@ -323,13 +641,22 @@ static int pruss_intc_probe(struct platform_device > *pdev) > } > } > > + err = of_property_read_u32(dev->of_node, "#interrupt-cells", > &num_cells); > + if (!err && num_cells == 5) > + intc->has_evtsel = true; > + > mutex_init(&intc->lock); > > + pm_runtime_enable(dev); > + pm_runtime_get_sync(dev); > + > pruss_intc_init(intc); > > irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); > - if (!irqchip) > - return -ENOMEM; > + if (!irqchip) { > + err = -ENOMEM; > + goto fail_alloc; > + } > > irqchip->irq_ack = pruss_intc_irq_ack; > irqchip->irq_mask = pruss_intc_irq_mask; > @@ -338,14 +665,24 @@ static int pruss_intc_probe(struct platform_device > *pdev) > irqchip->irq_release_resources = pruss_intc_irq_relres; > irqchip->irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state; > irqchip->irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state; > + irqchip->parent_device = dev; > irqchip->name = dev_name(dev); > intc->irqchip = irqchip; > > - /* always 64 events */ > - intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS, > - &pruss_intc_irq_domain_ops, intc); > - if (!intc->domain) > - return -ENOMEM; > + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) { > + intc->domain[i].intc = intc; > + intc->domain[i].id = i; > + /* always 64 events */ > + intc->domain[i].domain = irq_domain_add_linear(dev->of_node, > + MAX_PRU_SYS_EVENTS, &pruss_intc_irq_domain_ops, > + &intc->domain[i]); > + if (!intc->domain[i].domain) { > + while (--i >= 0) > + irq_domain_remove(intc->domain[i].domain); > + err = -ENOMEM; > + goto fail_alloc; > + } > + } > > for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { > irq = platform_get_irq_byname(pdev, irq_names[i]); > @@ -356,6 +693,7 @@ static int pruss_intc_probe(struct platform_device > *pdev) > > dev_err(dev, "platform_get_irq_byname failed for %s : %d\n", > irq_names[i], irq); > + err = irq; > goto fail_irq; > } > > @@ -372,13 +710,20 @@ static int pruss_intc_probe(struct platform_device > *pdev) > irq_set_chained_handler_and_data(intc->irqs[i], NULL, > NULL); > } > - irq_domain_remove(intc->domain); > - return irq; > + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) > + irq_domain_remove(intc->domain[i].domain); > + > +fail_alloc: > + pm_runtime_put(dev); > + pm_runtime_disable(dev); > + > + return err; > } > > static int pruss_intc_remove(struct platform_device *pdev) > { > struct pruss_intc *intc = platform_get_drvdata(pdev); > + struct device *dev = &pdev->dev; > unsigned int hwirq; > int i; > > @@ -388,9 +733,15 @@ static int pruss_intc_remove(struct platform_device > *pdev) > NULL); > } > > - for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) > - irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); > - irq_domain_remove(intc->domain); > + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) { > + for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) > + irq_dispose_mapping(irq_find_mapping( > + intc->domain[i].domain, hwirq)); > + irq_domain_remove(intc->domain[i].domain); > + } > + > + pm_runtime_put(dev); > + pm_runtime_disable(dev); > > return 0; > } > diff --git a/include/dt-bindings/interrupt-controller/ti-pruss.h > b/include/dt-bindings/interrupt-controller/ti-pruss.h > new file mode 100644 > index 000000000000..326a68c31bce > --- /dev/null > +++ b/include/dt-bindings/interrupt-controller/ti-pruss.h > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ > +/* > + * This header provides constants for the Texas Instruments Programmable > + * Realtime Unit Subsystem (PRUSS) interrupt controller. > + */ > + > +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H > +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H > + > +/* interrupt specifier for optional cell 1 */ > + > +#define TI_PRUSS_INTC_EVTSEL_ANY 0xffffffff > + > +/* interrupt specifier for cell #interrupt-cells - 1 */ > + > +/* host interrupt is connected to PRU cores, e.g. host events 0 and 1 */ > +#define TI_PRUSS_INTC_DOMAIN_PRU 0 > +/* host interrupt is connected to MCU's interrupt controller */ > +#define TI_PRUSS_INTC_DOMAIN_MCU 1 > +/* host interrupt is connected to DSP's interrupt controller */ > +#define TI_PRUSS_INTC_DOMAIN_DSP 2 > +/* host interrupt is connected to the auxillary PRU cores */ > +#define TI_PRUSS_INTC_DOMAIN_RTU_PRU 3 > +/* host interrupt is connected to the task managers */ > +#define TI_PRUSS_INTC_DOMAIN_TASK 4 > + > +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H */
On 8/12/19 2:39 PM, Suman Anna wrote: > Hi David, > > On 8/8/19 12:09 PM, David Lechner wrote: >> On 8/2/19 4:26 PM, Suman Anna wrote: >>> Point is different applications might use mapping differently as per >>> their firmware and driver/application design and their split across one >>> or more PRUs (design by contract). And we need to set this up at runtime >>> when the application driver is getting run. We will have either the Soft >>> UART or the Ethernet running at a time depending on the end goal desired >>> >>>> I have an idea that we can use multiple struct irq_domains to make >>>> this work in the existing IRQ framework, but it would be helpful to >>>> know more about the bigger picture first. >>> >>> Yeah, would be great if there is a way this can be solved without having >>> to introduce additional API. >>> >> >> >> Here is what I came up with to use existing IRQ APIs to implement event >> mapping. >> Basically it is the same as my previous suggestion [1], with the >> addition of >> multiple IRQ domains. > > First of all, many thanks for looking into the problem and providing > patches for the alternate solutions. If we were to not use any exported > functions, this approach does seem to be a viable solution. I am going > to play around with both [1] and this patch with all our existing > usecases and see if I run into any issues. > > So, w.r.t this patch compared to [1], is the multiple IRQ domain solving > anything specifically? Our main issue is the re-purposing of a event > (and its mapping depending on the application), and the same issue will > remain whether we have multiple domains or not. Also, now we would > expect an event to migrate between different domains based on its usage. The only thing using multiple IRQ domains gets us is that it allows us to have multiple IRQ descriptors (virq) for a single PRU event. In other words, if we needed to map a single system event to both a PRU core and the MCU interrupt controller at the same time, then we would need separate IRQ domains to do this. I we would never need to do something like this, then we don't the IRQ domains. Previously, you said "We can have two different applications use the same event with different mappings." So I took this to mean that the events would actually be mapped in hardware at the same time, but now I understand it to just mean that a single firmware blob could contain multiple mappings that contain the same events, but won't actually be used at the same time. So if this is the case, then we probably don't need to mess with IRQ domains. > >> >> The idea is that each external interrupt controller (or DMA controller, >> etc.) >> that is connected to the PRUSS interrupt controller is considered an >> interrupt >> domain. One of the objections to my previous patch was that we could >> only have >> one IRQ descriptor per event. Now we can have one descriptor per event per >> domain. >> >> I am still proposing that we use the interrupt-cells and identical vendor >> resource data structures in the PRU firmware be used to provide the mapping >> information. (As a side note, I still think it is important to include >> EVTSEL >> on AM18xx in order to fully describe the event.) > > W.r.t EVTSEL, it is a global value and applies to a range of events. I > have another equivalent register/functionality on most of the other SoCs > as well (a register in PRUSS_CFG space) that muxes standard events vs > MII_RT events. Again, that is limited to only a subset of all the system > events. So, should this continue to be a per event specifier, it will be > yet another mapping configuration data item (my idea was to manage this > once per application within the PRU remoteproc driver along with the > fwspec mapping). I guess it just seems a bit fragile to me to specify EVTSEL elsewhere. My thinking is that the first event registered that requires a specific EVTSEL value "wins" and if any other events are registered with a different EVTSEL value, then we will get an error. Likewise, if all users of a specific EVTSEL value are unmapped, then it is up for grabs for any value again. On the other hand, with a global value as you have proposed, we can just leave comments in the device tree and the firmware about which EVTSEL value is required for a specific event number. We won't be able to catch mistakes at runtime, but at least there will be something to remind us what we did wrong. So, I suppose that is good enough.
Hi David, On 8/13/19 9:26 AM, David Lechner wrote: > On 8/12/19 2:39 PM, Suman Anna wrote: >> Hi David, >> >> On 8/8/19 12:09 PM, David Lechner wrote: >>> On 8/2/19 4:26 PM, Suman Anna wrote: >>>> Point is different applications might use mapping differently as per >>>> their firmware and driver/application design and their split across one >>>> or more PRUs (design by contract). And we need to set this up at >>>> runtime >>>> when the application driver is getting run. We will have either the >>>> Soft >>>> UART or the Ethernet running at a time depending on the end goal >>>> desired >>>> >>>>> I have an idea that we can use multiple struct irq_domains to make >>>>> this work in the existing IRQ framework, but it would be helpful to >>>>> know more about the bigger picture first. >>>> >>>> Yeah, would be great if there is a way this can be solved without >>>> having >>>> to introduce additional API. >>>> >>> >>> >>> Here is what I came up with to use existing IRQ APIs to implement event >>> mapping. >>> Basically it is the same as my previous suggestion [1], with the >>> addition of >>> multiple IRQ domains. >> >> First of all, many thanks for looking into the problem and providing >> patches for the alternate solutions. If we were to not use any exported >> functions, this approach does seem to be a viable solution. I am going >> to play around with both [1] and this patch with all our existing >> usecases and see if I run into any issues. >> >> So, w.r.t this patch compared to [1], is the multiple IRQ domain solving >> anything specifically? Our main issue is the re-purposing of a event >> (and its mapping depending on the application), and the same issue will >> remain whether we have multiple domains or not. Also, now we would >> expect an event to migrate between different domains based on its usage. > > The only thing using multiple IRQ domains gets us is that it allows us to > have multiple IRQ descriptors (virq) for a single PRU event. In other > words, if we needed to map a single system event to both a PRU core and > the MCU interrupt controller at the same time, then we would need separate > IRQ domains to do this. I we would never need to do something like this, > then we don't the IRQ domains. Yeah, this is not a realistic usecase. A event can only be mapped to a single channel which in turn can be mapped to only a single output interrupt and we expect this to be processed by only a single entity even if it may be connected to multiple processors. That is going to be a system integration partitioning design choice. This is where the irqs-shared and irqs-reserved logic comes in, so that MPU doesn't deal with that interrupt line if it is expected to be handled by a different processor. > > Previously, you said "We can have two different applications use the same > event with different mappings." So I took this to mean that the events > would actually be mapped in hardware at the same time, but now I > understand it to just mean that a single firmware blob could contain > multiple mappings that contain the same events, but won't actually be used > at the same time. So if this is the case, then we probably don't need to > mess with IRQ domains. The different applications (like PRU Dual-EMAC or PRU Soft UART I mentioned earlier) will indeed be running at separate times, PRU cores are a very limited resource, so it is treated as an exclusive resource. The INTC is expected to be programmed as per the application running at a given time. We also expect the firmware blob to change as per the application. > > >> >>> >>> The idea is that each external interrupt controller (or DMA controller, >>> etc.) >>> that is connected to the PRUSS interrupt controller is considered an >>> interrupt >>> domain. One of the objections to my previous patch was that we could >>> only have >>> one IRQ descriptor per event. Now we can have one descriptor per >>> event per >>> domain. >>> >>> I am still proposing that we use the interrupt-cells and identical >>> vendor >>> resource data structures in the PRU firmware be used to provide the >>> mapping >>> information. (As a side note, I still think it is important to include >>> EVTSEL >>> on AM18xx in order to fully describe the event.) >> >> W.r.t EVTSEL, it is a global value and applies to a range of events. I >> have another equivalent register/functionality on most of the other SoCs >> as well (a register in PRUSS_CFG space) that muxes standard events vs >> MII_RT events. Again, that is limited to only a subset of all the system >> events. So, should this continue to be a per event specifier, it will be >> yet another mapping configuration data item (my idea was to manage this >> once per application within the PRU remoteproc driver along with the >> fwspec mapping). > > I guess it just seems a bit fragile to me to specify EVTSEL elsewhere. My > thinking is that the first event registered that requires a specific EVTSEL > value "wins" and if any other events are registered with a different EVTSEL > value, then we will get an error. Likewise, if all users of a specific > EVTSEL value are unmapped, then it is up for grabs for any value again. We usually expect an application to have possibly multiple events, and so all of them are expected to match if it is using multiple events within the range controlled by EVTSEL or the CFG register. It only needs to be programmed once if the application needs it. The first one to win introduces ordering issues in general. Anyway, for this solution to work in general, I am expecting the irq_create_fwspec_mapping()s to be per application, and they should be overwriting any previous configured values. > > On the other hand, with a global value as you have proposed, we can just > leave comments in the device tree and the firmware about which EVTSEL value > is required for a specific event number. We won't be able to catch mistakes > at runtime, but at least there will be something to remind us what we did > wrong. So, I suppose that is good enough. With the global value, I expect it to be a property of the client node alongside interrupts. The management and selection of this will be left to the PRU remoteproc driver. Encoding this on the firmware-side per event also seems a waste of memory. End of the day, it is going to be design contract with the application and firmware. regards Suman
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 3a1b8a93cfad..63cfc665be1e 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -9,6 +9,7 @@ #include <linux/irq.h> #include <linux/irqchip/chained_irq.h> +#include <linux/irqchip/irq-pruss-intc.h> #include <linux/irqdomain.h> #include <linux/module.h> #include <linux/of_device.h> @@ -24,8 +25,8 @@ /* minimum starting host interrupt number for MPU */ #define MIN_PRU_HOST_INT 2 -/* maximum number of system events */ -#define MAX_PRU_SYS_EVENTS 64 +/* maximum number of host interrupts */ +#define MAX_PRU_HOST_INT 10 /* PRU_ICSS_INTC registers */ #define PRU_INTC_REVID 0x0000 @@ -57,6 +58,16 @@ #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) #define PRU_INTC_HIER 0x1500 +/* CMR register bit-field macros */ +#define CMR_EVT_MAP_MASK 0xf +#define CMR_EVT_MAP_BITS 8 +#define CMR_EVT_PER_REG 4 + +/* HMR register bit-field macros */ +#define HMR_CH_MAP_MASK 0xf +#define HMR_CH_MAP_BITS 8 +#define HMR_CH_PER_REG 4 + /* HIPIR register bit-fields */ #define INTC_HIPIR_NONE_HINT 0x80000000 @@ -66,7 +77,9 @@ * @base: base virtual address of INTC register space * @irqchip: irq chip for this interrupt controller * @domain: irq domain for this interrupt controller + * @config_map: stored INTC configuration mapping data * @lock: mutex to serialize access to INTC + * @host_mask: indicate which HOST IRQs are enabled * @shared_intr: bit-map denoting if the MPU host interrupt is shared * @invalid_intr: bit-map denoting if host interrupt is not connected to MPU */ @@ -75,7 +88,9 @@ struct pruss_intc { void __iomem *base; struct irq_chip *irqchip; struct irq_domain *domain; + struct pruss_intc_config config_map; struct mutex lock; /* PRUSS INTC lock */ + u32 host_mask; u16 shared_intr; u16 invalid_intr; }; @@ -105,6 +120,267 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, return 0; } +static void pruss_intc_update_cmr(struct pruss_intc *intc, int evt, s8 ch) +{ + u32 idx, val; + + idx = evt / CMR_EVT_PER_REG; + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); + val &= ~(CMR_EVT_MAP_MASK << + ((evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS)); + val |= ch << ((evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS); + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); +} + +static void pruss_intc_update_hmr(struct pruss_intc *intc, int ch, s8 host) +{ + u32 idx, val; + + idx = ch / HMR_CH_PER_REG; + val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)); + val &= ~(HMR_CH_MAP_MASK << + ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS)); + val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS); + pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val); +} + +static struct pruss_intc *to_pruss_intc(struct device *pru_dev) +{ + struct device_node *np; + struct platform_device *pdev; + struct device *pruss_dev = pru_dev->parent; + struct pruss_intc *intc = ERR_PTR(-ENODEV); + + np = of_get_child_by_name(pruss_dev->of_node, "interrupt-controller"); + if (!np) { + dev_err(pruss_dev, "pruss does not have an interrupt-controller node\n"); + return intc; + } + + pdev = of_find_device_by_node(np); + if (!pdev) { + dev_err(pruss_dev, "no associated platform device\n"); + goto out; + } + + intc = platform_get_drvdata(pdev); + if (!intc) { + dev_err(pruss_dev, "pruss intc device probe failed?\n"); + intc = ERR_PTR(-EINVAL); + } + +out: + of_node_put(np); + return intc; +} + +/** + * pruss_intc_configure() - configure the PRUSS INTC + * @dev: pru device pointer + * @intc_config: PRU core-specific INTC configuration + * + * Configures the PRUSS INTC with the provided configuration from + * a PRU core. Any existing event to channel mappings or channel to + * host interrupt mappings are checked to make sure there are no + * conflicting configuration between both the PRU cores. The function + * is intended to be used only by the PRU remoteproc driver. + * + * Returns 0 on success, or a suitable error code otherwise + */ +int pruss_intc_configure(struct device *dev, + struct pruss_intc_config *intc_config) +{ + struct pruss_intc *intc; + int i, idx, ret; + s8 ch, host; + u64 sysevt_mask = 0; + u32 ch_mask = 0; + u32 host_mask = 0; + + intc = to_pruss_intc(dev); + if (IS_ERR(intc)) + return PTR_ERR(intc); + + mutex_lock(&intc->lock); + + /* + * configure channel map registers - each register holds map info + * for 4 events, with each event occupying the lower nibble in + * a register byte address in little-endian fashion + */ + for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + ch = intc_config->sysev_to_ch[i]; + if (ch < 0) + continue; + + /* check if sysevent already assigned */ + if (intc->config_map.sysev_to_ch[i] != PRU_INTC_FREE) { + dev_err(dev, "event %d (req. channel %d) already assigned to channel %d\n", + i, ch, intc->config_map.sysev_to_ch[i]); + ret = -EEXIST; + goto fail_evt; + } + + intc->config_map.sysev_to_ch[i] = ch; + pruss_intc_update_cmr(intc, i, ch); + sysevt_mask |= BIT_ULL(i); + ch_mask |= BIT(ch); + idx = i / CMR_EVT_PER_REG; + + dev_dbg(dev, "SYSEVT%d -> CH%d (CMR%d 0x%08x)\n", i, ch, idx, + pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); + } + + /* + * set host map registers - each register holds map info for + * 4 channels, with each channel occupying the lower nibble in + * a register byte address in little-endian fashion + */ + for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + host = intc_config->ch_to_host[i]; + if (host < 0) + continue; + + /* check if channel already assigned */ + if (intc->config_map.ch_to_host[i] != PRU_INTC_FREE) { + dev_err(dev, "channel %d (req. intr_no %d) already assigned to intr_no %d\n", + i, host, intc->config_map.ch_to_host[i]); + ret = -EEXIST; + goto fail_ch; + } + + /* check if host intr is already in use by other PRU */ + if (intc->host_mask & (1U << host)) { + dev_err(dev, "%s: host intr %d already in use\n", + __func__, host); + ret = -EEXIST; + goto fail_ch; + } + + intc->config_map.ch_to_host[i] = host; + pruss_intc_update_hmr(intc, i, host); + ch_mask |= BIT(i); + host_mask |= BIT(host); + idx = i / HMR_CH_PER_REG; + + dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", i, host, idx, + pruss_intc_read_reg(intc, PRU_INTC_HMR(idx))); + } + + dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n", + sysevt_mask, ch_mask, host_mask); + + /* enable system events, writing 0 has no-effect */ + pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + + /* enable host interrupts */ + for (i = 0; i < MAX_PRU_HOST_INT; i++) { + if (host_mask & BIT(i)) + pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i); + } + + /* global interrupt enable */ + pruss_intc_write_reg(intc, PRU_INTC_GER, 1); + + intc->host_mask |= host_mask; + + mutex_unlock(&intc->lock); + return 0; + +fail_ch: + while (--i >= 0) { + if (intc_config->ch_to_host[i] >= 0) { + intc->config_map.ch_to_host[i] = PRU_INTC_FREE; + pruss_intc_update_hmr(intc, i, 0); + } + } + i = ARRAY_SIZE(intc_config->sysev_to_ch); +fail_evt: + while (--i >= 0) { + if (intc_config->sysev_to_ch[i] >= 0) { + intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE; + pruss_intc_update_cmr(intc, i, 0); + } + } + mutex_unlock(&intc->lock); + return ret; +} +EXPORT_SYMBOL_GPL(pruss_intc_configure); + +/** + * pruss_intc_unconfigure() - unconfigure the PRUSS INTC + * @dev: pru device pointer + * @intc_config: PRU core specific INTC configuration + * + * Undo whatever was done in pruss_intc_configure() for a PRU core. + * It should be sufficient to just mark the resources free in the + * global map and disable the host interrupts and sysevents. + */ +int pruss_intc_unconfigure(struct device *dev, + struct pruss_intc_config *intc_config) +{ + struct pruss_intc *intc; + int i; + s8 ch, host; + u64 sysevt_mask = 0; + u32 host_mask = 0; + + intc = to_pruss_intc(dev); + if (IS_ERR(intc)) + return PTR_ERR(intc); + + mutex_lock(&intc->lock); + + for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + ch = intc_config->sysev_to_ch[i]; + if (ch < 0) + continue; + + /* mark sysevent free in global map */ + intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE; + sysevt_mask |= BIT_ULL(i); + /* clear the map using reset value 0 */ + pruss_intc_update_cmr(intc, i, 0); + } + + for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + host = intc_config->ch_to_host[i]; + if (host < 0) + continue; + + /* mark channel free in global map */ + intc->config_map.ch_to_host[i] = PRU_INTC_FREE; + host_mask |= BIT(host); + /* clear the map using reset value 0 */ + pruss_intc_update_hmr(intc, i, 0); + } + + dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n", + sysevt_mask, host_mask); + + /* disable system events, writing 0 has no-effect */ + pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask)); + /* clear any pending status */ + pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); + pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + + /* disable host interrupts */ + for (i = 0; i < MAX_PRU_HOST_INT; i++) { + if (host_mask & BIT(i)) + pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i); + } + + intc->host_mask &= ~host_mask; + mutex_unlock(&intc->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_intc_unconfigure); + static void pruss_intc_init(struct pruss_intc *intc) { int i; @@ -290,6 +566,12 @@ static int pruss_intc_probe(struct platform_device *pdev) mutex_init(&intc->lock); + for (i = 0; i < ARRAY_SIZE(intc->config_map.sysev_to_ch); i++) + intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE; + + for (i = 0; i < ARRAY_SIZE(intc->config_map.ch_to_host); i++) + intc->config_map.ch_to_host[i] = PRU_INTC_FREE; + pruss_intc_init(intc); irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h new file mode 100644 index 000000000000..daffc048b303 --- /dev/null +++ b/include/linux/irqchip/irq-pruss-intc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * PRU-ICSS sub-system private interfaces + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna <s-anna@ti.com> + */ + +#ifndef __LINUX_IRQ_PRUSS_INTC_H +#define __LINUX_IRQ_PRUSS_INTC_H + +/* maximum number of system events */ +#define MAX_PRU_SYS_EVENTS 64 + +/* maximum number of interrupt channels */ +#define MAX_PRU_CHANNELS 10 + +/* use -1 to mark unassigned events and channels */ +#define PRU_INTC_FREE -1 + +/** + * struct pruss_intc_config - INTC configuration info + * @sysev_to_ch: system events to channel mapping information + * @ch_to_host: interrupt channel to host interrupt information + */ +struct pruss_intc_config { + s8 sysev_to_ch[MAX_PRU_SYS_EVENTS]; + s8 ch_to_host[MAX_PRU_CHANNELS]; +}; + +int pruss_intc_configure(struct device *dev, + struct pruss_intc_config *intc_config); +int pruss_intc_unconfigure(struct device *dev, + struct pruss_intc_config *intc_config); + +#endif /* __LINUX_IRQ_PRUSS_INTC_H */