Message ID | 20190919193141.7865-34-miquel.raynal@bootlin.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
Return-Path: <SRS0=Ih/8=XO=lists.infradead.org=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 61EC114DB for <patchwork-linux-arm@patchwork.kernel.org>; Thu, 19 Sep 2019 19:53:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F58C20678 for <patchwork-linux-arm@patchwork.kernel.org>; Thu, 19 Sep 2019 19:53:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="aj4vPhJa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3F58C20678 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org |
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Introduce the generic ECC engine abstraction
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expand
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diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index a0f23051cc21..d2433d912aee 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -5586,6 +5586,13 @@ static int nand_scan_tail(struct nand_chip *chip) break; } + /* + * If there is no specific user request for the ECC engine provider, use + * the one chosen by the driver being instantiated. + */ + chip->base.ecc.defaults.provider = ecc->mode; + chip->base.ecc.defaults.algo = ecc->algo; + ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner); if (ret) goto err_nand_manuf_cleanup;
The raw NAND layer may want to use one or another ECC provider if the user did not explicitly broadcasted his choice through the DT. Raw NAND controllers can also want to force these values. In any case, the NAND core must be able to know their preference and this works by letting subsystems/drivers filling/changing the "defaults" ECC structure. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/mtd/nand/raw/nand_base.c | 7 +++++++ 1 file changed, 7 insertions(+)