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Tue, 24 Sep 2019 07:47:00 +0000 From: To: , , , , , Subject: [PATCH v2 21/22] mtd: spi-nor: Update sr2_bit7_quad_enable() Thread-Topic: [PATCH v2 21/22] mtd: spi-nor: Update sr2_bit7_quad_enable() Thread-Index: AQHVcqw/7/hvqSeZZk2fV5BDSeD29Q== Date: Tue, 24 Sep 2019 07:47:00 +0000 Message-ID: <20190924074533.6618-22-tudor.ambarus@microchip.com> References: <20190924074533.6618-1-tudor.ambarus@microchip.com> In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0101CA0082.eurprd01.prod.exchangelabs.com (2603:10a6:800:1f::50) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fb1f1616-d389-4068-23df-08d740c361be x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(2017052603328)(7193020); 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Do the read back test on all the eight bits of the Status Register, not just the QE one. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8fd1c04f75d9..a53e2cdc564c 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2038,7 +2038,7 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) } /** - * sr2_bit7_quad_enable() - set QE bit in Status Register 2. + * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. * @nor: pointer to a 'struct spi_nor' * * Set the Quad Enable (QE) bit in the Status Register 2. @@ -2049,10 +2049,11 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) * * Return: 0 on success, -errno otherwise. */ -static int sr2_bit7_quad_enable(struct spi_nor *nor) +static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) { u8 *sr2 = nor->bouncebuf; int ret; + u8 sr2_written; /* Check current Quad Enable bit value. */ ret = spi_nor_read_sr2(nor, sr2); @@ -2069,13 +2070,15 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) if (ret) return ret; + sr2_written = *sr2; + /* Read back and check it. */ ret = spi_nor_read_sr2(nor, sr2); if (ret) return ret; - if (!(*sr2 & SR2_QUAD_EN_BIT7)) { - dev_err(nor->dev, "SR2 Quad bit not set\n"); + if (*sr2 != sr2_written) { + dev_err(nor->dev, "Read back test failed\n"); return -EIO; } @@ -3649,7 +3652,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, case BFPT_DWORD15_QER_SR2_BIT7: nor->flags &= ~SNOR_F_HAS_16BIT_SR; - flash->quad_enable = sr2_bit7_quad_enable; + flash->quad_enable = spi_nor_sr2_bit7_quad_enable; break; case BFPT_DWORD15_QER_SR2_BIT1: