| Message ID | 20191004012525.26647-2-chris.packham@alliedtelesis.co.nz (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | gpio: brcm: XGS iProc GPIO driver | expand |
On Fri, Oct 04, 2019 at 02:25:24PM +1300, Chris Packham wrote: > This GPIO controller is present on a number of Broadcom switch ASICs > with integrated SoCs. It is similar to the nsp-gpio and iproc-gpio > blocks but different enough to require a separate driver. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > .../bindings/gpio/brcm,xgs-iproc.txt | 41 +++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.txt Please make this a DT schema. > > diff --git a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.txt b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.txt > new file mode 100644 > index 000000000000..328b844c82dc > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.txt > @@ -0,0 +1,41 @@ > +Broadcom XGS iProc GPIO controller > + > +This controller is the Chip Common A GPIO present on a number of Broadcom > +switch ASICs with integrated SoCs. > + > +Required properties: > +- compatible: > + Must be "brcm,iproc-gpio-cca" > + > +- reg: > + The first region defines the base I/O address containing > + the GPIO controller registers. The second region defines > + the I/O address containing the Chip Common A interrupt > + registers. > + > +Optional properties: > + > +- interrupts: > + The interrupt shared by all GPIO lines for this controller. > + > +- #interrupt-cells: > + Should be <2>. The first cell is the GPIO number, the second should specify > + flags. > + > + See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt > + > +- interrupt-controller: > + Marks the device node as an interrupt controller > + > +Example: > + gpioa: gpio@18000060 { > + compatible = "brcm,iproc-gpio-cca"; > + #gpio-cells = <2>; Not documented... > + reg = <0x18000060 0x50>, > + <0x18000000 0x50>; > + ngpios = <12>; Not documented. > + gpio-controller; Not documented. > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; > + }; > -- > 2.23.0 >
diff --git a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.txt b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.txt new file mode 100644 index 000000000000..328b844c82dc --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.txt @@ -0,0 +1,41 @@ +Broadcom XGS iProc GPIO controller + +This controller is the Chip Common A GPIO present on a number of Broadcom +switch ASICs with integrated SoCs. + +Required properties: +- compatible: + Must be "brcm,iproc-gpio-cca" + +- reg: + The first region defines the base I/O address containing + the GPIO controller registers. The second region defines + the I/O address containing the Chip Common A interrupt + registers. + +Optional properties: + +- interrupts: + The interrupt shared by all GPIO lines for this controller. + +- #interrupt-cells: + Should be <2>. The first cell is the GPIO number, the second should specify + flags. + + See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + +- interrupt-controller: + Marks the device node as an interrupt controller + +Example: + gpioa: gpio@18000060 { + compatible = "brcm,iproc-gpio-cca"; + #gpio-cells = <2>; + reg = <0x18000060 0x50>, + <0x18000000 0x50>; + ngpios = <12>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + };
This GPIO controller is present on a number of Broadcom switch ASICs with integrated SoCs. It is similar to the nsp-gpio and iproc-gpio blocks but different enough to require a separate driver. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- .../bindings/gpio/brcm,xgs-iproc.txt | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.txt