From patchwork Fri Oct 4 11:59:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 11174307 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E513913B1 for ; Fri, 4 Oct 2019 12:02:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C249B20862 for ; Fri, 4 Oct 2019 12:02:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="pm/FeZzB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C249B20862 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tyce4iUwlwDU8i2MkAvs7mqep37CM1oMunLJFsMR+SA=; b=pm/FeZzBGKD4ha WuQHld4Ph4irsfNyqdbDsGW6DMP8VuRyEOrT8sTEkMkYM/aDz0kYBigv+4lemPk8gIIvk2f1dcq9p EVFX4y0eHxIlMoDY88et15cQRsJq6coE5YRE+aqLXsF4pWF4wTyq44rc0JK1jZqY5B8xEldRwUj0s XfIMZ5+wdNa6LUuCJHy5C/5e+vy0jiHbguCJFN348wRdeXd+L6OHPstxGN6IvBCX92XvfdbSCMx9r sPOooP9S/u2+b4GaRhHzAEzYkCzzW5yjsioUlF6x66649CRu+JB/DBxXH6Ue69xXKz5rXz4Lj68+b IT+M5W6nEwFMLcHGZ0Vg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iGMIN-00005P-7B; Fri, 04 Oct 2019 12:02:51 +0000 Received: from 7.mo173.mail-out.ovh.net ([46.105.44.159]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iGMGl-0006zy-EG for linux-arm-kernel@lists.infradead.org; Fri, 04 Oct 2019 12:01:13 +0000 Received: from player792.ha.ovh.net (unknown [10.109.146.137]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id E0B1711BA5E for ; Fri, 4 Oct 2019 14:01:08 +0200 (CEST) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player792.ha.ovh.net (Postfix) with ESMTPSA id EBFDBAA65C67; Fri, 4 Oct 2019 12:00:51 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: linux-mtd@lists.infradead.org, Tudor Ambarus Subject: [PATCH 05/16] mtd: spi-nor: aspeed: Limit the maximum SPI frequency Date: Fri, 4 Oct 2019 13:59:08 +0200 Message-Id: <20191004115919.20788-6-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191004115919.20788-1-clg@kaod.org> References: <20191004115919.20788-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 3784149587467340723 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrhedugdegudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191004_050111_644127_CB9C76BF X-CRM114-Status: GOOD ( 17.45 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [46.105.44.159 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Vignesh Raghavendra , linux-aspeed@lists.ozlabs.org, Andrew Jeffery , Richard Weinberger , Marek Vasut , Joel Stanley , Miquel Raynal , Brian Norris , David Woodhouse , linux-arm-kernel@lists.infradead.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The read training algorithm can choose a 100MHz SPI frequency which might be a bit too high for dual output IO on some chips, for the W25Q256 on palmetto for instance. The MX66L1G45G on witherspoon should be fine though. Also, the second chip of the FMC controller does not get any optimize settings for reads. Only the first is configured by U-Boot. To fix these two issues, we introduce a "spi-max-frequency" property in the device tree which will be used to cap the read training algorithm. It is now considered safe to run the read training on the FMC controller chips as well. By default, the frequency setting is 50MHz. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery --- drivers/mtd/spi-nor/aspeed-smc.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index 155c407c2bdf..1c1822a13407 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -58,6 +58,7 @@ static const struct aspeed_smc_info fmc_2400_info = { .ctl0 = 0x10, .timing = 0x94, .set_4b = aspeed_smc_chip_set_4b, + .optimize_read = aspeed_smc_optimize_read, }; static const struct aspeed_smc_info spi_2400_info = { @@ -79,6 +80,7 @@ static const struct aspeed_smc_info fmc_2500_info = { .ctl0 = 0x10, .timing = 0x94, .set_4b = aspeed_smc_chip_set_4b, + .optimize_read = aspeed_smc_optimize_read, }; static const struct aspeed_smc_info spi_2500_info = { @@ -110,6 +112,7 @@ struct aspeed_smc_chip { u32 ctl_val[smc_max]; /* control settings */ enum aspeed_smc_flash_type type; /* what type of flash */ struct spi_nor nor; + u32 clk_rate; }; struct aspeed_smc_controller { @@ -126,6 +129,8 @@ struct aspeed_smc_controller { struct aspeed_smc_chip *chips[0]; /* pointers to attached chips */ }; +#define ASPEED_SPI_DEFAULT_FREQ 50000000 + /* * SPI Flash Configuration Register (AST2500 SPI) * or @@ -1002,11 +1007,8 @@ static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip) dev_info(controller->dev, "read control register: %08x\n", chip->ctl_val[smc_read]); - /* - * TODO: get max freq from chip - */ if (optimize_read && info->optimize_read) - info->optimize_read(chip, 104000000); + info->optimize_read(chip, chip->clk_rate); return 0; } @@ -1060,6 +1062,13 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller, break; } + if (of_property_read_u32(child, "spi-max-frequency", + &chip->clk_rate)) { + chip->clk_rate = ASPEED_SPI_DEFAULT_FREQ; + } + dev_info(dev, "Using %d MHz SPI frequency\n", + chip->clk_rate / 1000000); + chip->controller = controller; chip->ctl = controller->regs + info->ctl0 + cs * 4; chip->cs = cs;