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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 4 Oct 2019 13:09:40 +0100 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x94C9dQO53870610 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Oct 2019 12:09:39 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0BA02AE051; Fri, 4 Oct 2019 12:09:39 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E984CAE055; Fri, 4 Oct 2019 12:09:38 +0000 (GMT) Received: from smtp.tls.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 4 Oct 2019 12:09:38 +0000 (GMT) Received: from yukon.kaod.org.com (sig-9-145-169-184.de.ibm.com [9.145.169.184]) by smtp.tls.ibm.com (Postfix) with ESMTP id D932F220204; Fri, 4 Oct 2019 14:09:37 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: linux-mtd@lists.infradead.org, Tudor Ambarus Subject: [PATCH 15/16] mtd: spi-nor: aspeed: Introduce a HCLK mask for training Date: Fri, 4 Oct 2019 14:09:33 +0200 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191004120934.21662-1-clg@kaod.org> References: <20191004115919.20788-1-clg@kaod.org> <20191004120934.21662-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19100412-4275-0000-0000-0000036E030C X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100412-4276-0000-0000-000038810CF5 Message-Id: <20191004120934.21662-2-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-04_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=713 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910040113 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191004_050948_377804_DA79FC06 X-CRM114-Status: GOOD ( 22.49 ) X-Spam-Score: 0.3 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [148.163.158.5 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 1.0 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Vignesh Raghavendra , linux-aspeed@lists.ozlabs.org, Andrew Jeffery , Richard Weinberger , Marek Vasut , Joel Stanley , Miquel Raynal , Brian Norris , David Woodhouse , linux-arm-kernel@lists.infradead.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The AST2600 handles more HCLK divisors than its predecessors. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery --- drivers/mtd/spi-nor/aspeed-smc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index 85b7ff3bcc91..5fa9956d183e 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -41,6 +41,7 @@ struct aspeed_smc_info { u8 we0; /* shift for write enable bit for CE0 */ u8 ctl0; /* offset in regs of ctl for CE0 */ u8 timing; /* offset in regs of timing */ + u32 hclk_mask; /* clock frequency mask in CEx Control reg */ u32 hdiv_max; /* Max HCLK divisor on read timing reg */ void (*set_4b)(struct aspeed_smc_chip *chip); @@ -75,6 +76,7 @@ static const struct aspeed_smc_info fmc_2400_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hclk_mask = 0xfffff0ff, .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, @@ -91,6 +93,7 @@ static const struct aspeed_smc_info spi_2400_info = { .we0 = 0, .ctl0 = 0x04, .timing = 0x14, + .hclk_mask = 0xfffff0ff, .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b_spi_2400, .optimize_read = aspeed_smc_optimize_read, @@ -105,6 +108,7 @@ static const struct aspeed_smc_info fmc_2500_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hclk_mask = 0xfffff0ff, .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, @@ -121,6 +125,7 @@ static const struct aspeed_smc_info spi_2500_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hclk_mask = 0xfffff0ff, .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, @@ -1058,7 +1063,7 @@ static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE); /* Establish our read mode with freq field set to 0 (HCLK/16) */ - chip->ctl_val[smc_read] = save_read_val & 0xfffff0ff; + chip->ctl_val[smc_read] = save_read_val & info->hclk_mask; /* Check if calibration data is suitable */ if (!aspeed_smc_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {