| Message ID | 20191004185234.31471-3-pasha.tatashin@soleen.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: MMU enabled kexec relocation | expand |
Hi Pavel, On 04/10/2019 19:52, Pavel Tatashin wrote: > ttbr0 should be set to the beginning of pgdp, however, currently > in create_safe_exec_page it is set to pgdp after pgd_offset_raw(), > which works by accident. > > Fixes: 0194e760f7d2 ("arm64: hibernate: avoid potential TLB conflict") (That was a 'break before make' fix, the affected code comes from: 82869ac57b5d (""arm64: kernel: Add support for hibernate/suspend-to-disk)) But, it works in all one circumstances its used: we know all the top bits will be zero. I agree its by accident and we should fix it. I don't think we should send it to stable. Please drop the fixes tag, with that: Reviewed-by: James Morse <james.morse@arm.com> Thanks, James [0] https://lore.kernel.org/linux-arm-kernel/ddd81093-89fc-5146-0b33-ad3bd9a1c10c@arm.com/
On 19-10-11 19:17:22, James Morse wrote: > > Fixes: 0194e760f7d2 ("arm64: hibernate: avoid potential TLB conflict") > > (That was a 'break before make' fix, the affected code comes from: > 82869ac57b5d (""arm64: kernel: Add support for hibernate/suspend-to-disk)) > > But, it works in all one circumstances its used: we know all the top bits will be zero. > I agree its by accident and we should fix it. > > I don't think we should send it to stable. > Please drop the fixes tag, with that: OK > Reviewed-by: James Morse <james.morse@arm.com> Thank you! Pasha
diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c index e0a7fce0e01c..d52f69462c8f 100644 --- a/arch/arm64/kernel/hibernate.c +++ b/arch/arm64/kernel/hibernate.c @@ -201,6 +201,7 @@ static int create_safe_exec_page(void *src_start, size_t length, gfp_t mask) { int rc = 0; + pgd_t *trans_pgd; pgd_t *pgdp; pud_t *pudp; pmd_t *pmdp; @@ -215,7 +216,8 @@ static int create_safe_exec_page(void *src_start, size_t length, memcpy((void *)dst, src_start, length); __flush_icache_range(dst, dst + length); - pgdp = pgd_offset_raw(allocator(mask), dst_addr); + trans_pgd = allocator(mask); + pgdp = pgd_offset_raw(trans_pgd, dst_addr); if (pgd_none(READ_ONCE(*pgdp))) { pudp = allocator(mask); if (!pudp) { @@ -262,7 +264,7 @@ static int create_safe_exec_page(void *src_start, size_t length, */ cpu_set_reserved_ttbr0(); local_flush_tlb_all(); - write_sysreg(phys_to_ttbr(virt_to_phys(pgdp)), ttbr0_el1); + write_sysreg(phys_to_ttbr(virt_to_phys(trans_pgd)), ttbr0_el1); isb(); *phys_dst_addr = virt_to_phys((void *)dst);
ttbr0 should be set to the beginning of pgdp, however, currently in create_safe_exec_page it is set to pgdp after pgd_offset_raw(), which works by accident. Fixes: 0194e760f7d2 ("arm64: hibernate: avoid potential TLB conflict") Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com> --- arch/arm64/kernel/hibernate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)