diff mbox series

[9/9] ARM: dts: imx6qdl-apf6dev: use DRM bindings

Message ID 20191022131655.25737-10-sebastien.szymanski@armadeus.com (mailing list archive)
State Accepted
Headers show
Series ARM: dts: update APF6 / APF6Dev | expand

Commit Message

Sébastien Szymanski Oct. 22, 2019, 1:16 p.m. UTC
Describe the parallel LCD using simple panel driver.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
---
 arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 50 ++++++++++++++------------
 1 file changed, 28 insertions(+), 22 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index f617089be9cc..0aae958640db 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -21,33 +21,27 @@ 
 
 	disp0 {
 		compatible = "fsl,imx-parallel-display";
-		interface-pix-fmt = "bgr666";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu1_disp1>;
-
-		display-timings {
-			lw700 {
-				clock-frequency = <33000033>;
-				hactive = <800>;
-				vactive = <480>;
-				hback-porch = <96>;
-				hfront-porch = <96>;
-				vback-porch = <20>;
-				vfront-porch = <21>;
-				hsync-len = <64>;
-				vsync-len = <4>;
-				hsync-active = <1>;
-				vsync-active = <1>;
-				de-active = <1>;
-				pixelclk-active = <1>;
-			};
-		};
+		pinctrl-0 = <&pinctrl_ipu1_disp0>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
 
-		port {
 			display_in: endpoint {
 				remote-endpoint = <&ipu1_di0_disp0>;
 			};
 		};
+
+		port@1 {
+			reg = <1>;
+
+			display_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
 	};
 
 	gpio-keys {
@@ -76,6 +70,18 @@ 
 		};
 	};
 
+	panel {
+		compatible = "armadeus,st0700-adapt";
+		power-supply = <&reg_3p3v>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&display_out>;
+			};
+		};
+	};
+
 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "3P3V";
@@ -351,7 +357,7 @@ 
 		>;
 	};
 
-	pinctrl_ipu1_disp1: ipu1disp1grp {
+	pinctrl_ipu1_disp0: ipu1disp0grp {
 		fsl,pins = <
 			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x100b1
 			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x100b1